Commit Graph

179 Commits

Author SHA1 Message Date
marius
bcdda8018e - Add entries for the more prominent members of the Digi International
Neo series, which are based on Exar PCI chips.
- Mark some unused parameters as such.
- Fix style

MFC after:	3 days
2015-12-29 17:07:28 +00:00
marius
9f8cae598d - Add an entry for the SIIG Cyber 2SP1 PCIe adapter, which is based
on an Oxford Semiconductor OX16PCI954 but uses only two ports and
  a non-default clock rate.
- Fix style/whitespace

PR:		176407
MFC after:	3 days
2015-12-28 20:24:08 +00:00
loos
25cfd6ba23 puc(4): Add an entry for the Feasso PCI FPP-02 2S1P card.
MFC after:	1 week
2015-01-02 22:45:55 +00:00
rpaulo
7167b162bc puc(4): add an entry for the Oxford Semiconductor OXPCIe952 1S1P card.
Submitted by:	Alex Burlyga <alex.burlyga.ietf at gmail.com>
MFC after:	1 week
2014-10-23 18:03:27 +00:00
hselasky
35b126e324 Pull in r267961 and r267973 again. Fix for issues reported will follow. 2014-06-28 03:56:17 +00:00
gjb
fc21f40567 Revert r267961, r267973:
These changes prevent sysctl(8) from returning proper output,
such as:

 1) no output from sysctl(8)
 2) erroneously returning ENOMEM with tools like truss(1)
    or uname(1)
 truss: can not get etype: Cannot allocate memory
2014-06-27 22:05:21 +00:00
hselasky
bd1ed65f0f Extend the meaning of the CTLFLAG_TUN flag to automatically check if
there is an environment variable which shall initialize the SYSCTL
during early boot. This works for all SYSCTL types both statically and
dynamically created ones, except for the SYSCTL NODE type and SYSCTLs
which belong to VNETs. A new flag, CTLFLAG_NOFETCH, has been added to
be used in the case a tunable sysctl has a custom initialisation
function allowing the sysctl to still be marked as a tunable. The
kernel SYSCTL API is mostly the same, with a few exceptions for some
special operations like iterating childrens of a static/extern SYSCTL
node. This operation should probably be made into a factored out
common macro, hence some device drivers use this. The reason for
changing the SYSCTL API was the need for a SYSCTL parent OID pointer
and not only the SYSCTL parent OID list pointer in order to quickly
generate the sysctl path. The motivation behind this patch is to avoid
parameter loading cludges inside the OFED driver subsystem. Instead of
adding special code to the OFED driver subsystem to post-load tunables
into dynamically created sysctls, we generalize this in the kernel.

Other changes:
- Corrected a possibly incorrect sysctl name from "hw.cbb.intr_mask"
to "hw.pcic.intr_mask".
- Removed redundant TUNABLE statements throughout the kernel.
- Some minor code rewrites in connection to removing not needed
TUNABLE statements.
- Added a missing SYSCTL_DECL().
- Wrapped two very long lines.
- Avoid malloc()/free() inside sysctl string handling, in case it is
called to initialize a sysctl from a tunable, hence malloc()/free() is
not ready when sysctls from the sysctl dataset are registered.
- Bumped FreeBSD version to indicate SYSCTL API change.

MFC after:	2 weeks
Sponsored by:	Mellanox Technologies
2014-06-27 16:33:43 +00:00
marius
486a5ea805 Correct a typo in a device description added in r264257. 2014-04-15 19:58:05 +00:00
marius
e6badc5b2e Refine r264257; given that I later on decided to nuke the wildcard for
the Sunix 0x1999 line of chips there actually is no need to explicitly
keep puc(4) from attaching to the single port version anymore.
2014-04-10 21:03:46 +00:00
marius
d636882622 Distinguish between the different variants and configurations of Sunix
{MIO,SER}5xxxx chips instead of treating all of them as PUC_PORT_2S.
Among others, this fixes the hang seen when trying to probe the none-
existent second UART on an actually 1-port chip.

Obtained from:	NetBSD (BAR layouts)
MFC after:	3 days
Sponsored by:	Bally Wulff Games & Entertainment GmbH
2014-04-08 07:32:32 +00:00
rstone
24e43b4e62 Add MSI support to puc(9)
Add support for MSI interrupts in the puc(9) driver.  By default the driver
will prefer MSI interrupts to legacy interrupts.  A tunable,
hw.puc.msi_disable, has been added to force the allocation of legacy
interrupts.

Reviewed by:	jhb@
MFC after:	2 weeks
Sponsored by:	Sandvine Inc.
2014-03-13 15:57:25 +00:00
pluknet
39742cda03 Clean up -Wheader-guard warnings.
Submitted by:	<dt71@gmx.com>
MFC after:	3 days
X-MFC with:	r251848
2013-06-17 20:11:04 +00:00
marius
546690b392 All of Oxford/PLX OX16PCI954, OXm16PCI954 and OXu16PCI954 share the
exact same (subsystem) device and vendor IDs. However, the reference
design for the OXu16PCI954 uses a 14.7456 MHz clock (as does the EXSYS
EX-41098-2 equipped with these), while at least the OX16PCI954 defaults
to a 1.8432 MHz one. According to the datasheets of these chips, the
only difference in PCI configuration space is that OXu16PCI954 have
a revision ID of 1 while the other two are at 0. So employ the latter
for determining the default clock rates of this family.
Note that one might think that the actual clock could be derived from
the Clock Prescaler Register (CPR) of these chips. Unfortunately, this
is not that case and its use and content are orthogonal to the frequency
of the crystal employed.
Tested with an EXSYS EX-41098-2, which identifies and attaches as:
pcib4@pci0:19:0:0:      class=0x060400 card=0x02dd1014 chip=0x10801b21
rev=0x03 hdr=0x01
    vendor     = 'ASMedia Technology Inc.'
    device     = 'ASM1083/1085 PCIe to PCI Bridge'
    class      = bridge
    subclass   = PCI-PCI
puc0@pci0:20:4:0:       class=0x070006 card=0x00001415 chip=0x95011415
rev=0x01 hdr=0x00
    vendor     = 'Oxford Semiconductor Ltd'
    device     = 'OX16PCI954 (Quad 16950 UART) function 0 (Uart)'
    class      = simple comms
    subclass   = UART
puc1@pci0:20:4:1:       class=0x068000 card=0x00001415 chip=0x95111415
rev=0x01 hdr=0x00
    vendor     = 'Oxford Semiconductor Ltd'
    device     = 'OX16PCI954 (Quad 16950 UART) function 1 (8bit bus)'
    class      = bridge
puc2@pci0:20:8:0:       class=0x070006 card=0x00001415 chip=0x95011415
rev=0x01 hdr=0x00
    vendor     = 'Oxford Semiconductor Ltd'
    device     = 'OX16PCI954 (Quad 16950 UART) function 0 (Uart)'
    class      = simple comms
    subclass   = UART
puc3@pci0:20:8:1:       class=0x068000 card=0x00001415 chip=0x95111415
rev=0x01 hdr=0x00
    vendor     = 'Oxford Semiconductor Ltd'
    device     = 'OX16PCI954 (Quad 16950 UART) function 1 (8bit bus)'
    class      = bridge

pci20: <ACPI PCI bus> on pcib4
puc0: <Oxford Semiconductor OX16PCI954 UARTs> port 0x5000-0x501f,
0x5020-0x503f mem 0xc6000000-0xc6000fff,0xc6001000-0xc6001fff irq 16 at
device 4.0 on pci20
uart1: <16950 or compatible> at port 1 on puc0
uart2: <16950 or compatible> at port 2 on puc0
uart3: <16950 or compatible> at port 3 on puc0
uart4: <16950 or compatible> at port 4 on puc0
puc1: <Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)> port
0x5040-0x505f,0x5060-0x507f mem 0xc6002000-0xc6002fff,0xc6003000-0xc6003fff
irq 16 at device 4.1 on pci20
puc2: <Oxford Semiconductor OX16PCI954 UARTs> port 0x5080-0x509f,
0x50a0-0x50bf mem 0xc6004000-0xc6004fff,0xc6005000-0xc6005fff irq 16 at
device 8.0 on pci20
uart5: <16950 or compatible> at port 1 on puc2
uart6: <16950 or compatible> at port 2 on puc2
uart7: <16950 or compatible> at port 3 on puc2
uart8: <16950 or compatible> at port 4 on puc2
puc3: <Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)> port
0x50c0-0x50df,0x50e0-0x50ff mem 0xc6006000-0xc6006fff,0xc6007000-0xc6007fff
irq 16 at device 8.1 on pci20

MFC after:	2 weeks
2013-06-13 22:13:41 +00:00
marius
6f97de1744 Fix whitespace and normalize some entries. 2013-06-13 21:47:22 +00:00
rstone
9e3df2d114 Correct the definition for Exar XR17V258IV: we must use a config_function
to specify the offset into the PCI memory spare at which each serial port
will find its registers.  This was already done for other Exar PCI serial
devices; it was accidentally omitted for this specific device.

Sponsored by:	Sandvine Incorporated
MFC after:	1 week
2013-03-18 19:22:51 +00:00
rstone
9613a0ac27 Add support for Exar XR17V358 8-port serial device to puc(4)
Reviewed by:	marius
Sponsored by:	Sandvine Inc.
MFC after:	1 week
2013-03-15 19:58:44 +00:00
marius
8e8db171cb - Apparently, r186520 was just wrong and the clock of Oxford OX16PCI958 is
neither DEFAULT_RCLK * 2 nor DEFAULT_RCLK * 10 but plain DEFAULT_RCLK
  and there's no (open) source indicating otherwise. This was tested with
  an EXSYS EX-41098-2, whose clock is not configurable and identifies as:
  puc0@pci0:5:1:0:        class=0x070200 card=0x06711415 chip=0x95381415 rev=0x01 hdr=0x00
      vendor     = 'Oxford Semiconductor Ltd'
      class      = simple comms
      subclass   = multiport serial

  Note that this exactly matches the card mentioned in PR 129665 so no
  sub-device/sub-vendor based quirking of the latter is possible. So maybe
  we should grow some sort of tunable, in case non-default cards such as
  the latter aren't configurable either (this also wouldn't be the first
  time an allegedly tested commit turns out to be wrong though).
- Make the TiMedia tables const.

MFC after:	1 week
2013-03-01 20:16:06 +00:00
jhb
f8c0225fe0 Do not require a filter-only interrupt handler for puc ports that are not
serial devices (such as printer ports).  This allows ppc devices attached
to puc to correctly setup an interrupt handler and work.

Tested by:	Andre Albsmeier  Andre.Albsmeier@siemens.com
MFC after:	1 week
2013-01-15 20:13:25 +00:00
eadler
04e7b32045 Add support for Advantech PCI-1602 RS-485/RS-422 serial card
PR:		kern/169726
Submitted by:	Jan Mikkelsen <janm@transactionware.com>
Approved by:	cperciva (implicit)
MFC after:	5 days
2012-11-09 01:51:06 +00:00
eadler
ec8c8f8e30 Add support for SIIG Cyber Serial Dual PCI 16C850
Submitted by:	David Boyd David.Boyd@insightbb.com
Approved by:	cperciva
MFC after:	3 days
2012-08-05 19:37:18 +00:00
eadler
58d5fe0bdc Add additional Perle Speed LE serial cards
PR:		kern/168816
Submitted by:	Dennis Oyama <doyama@perle.com>
Approved by:	cperciva
MFC after:	1 week
2012-08-05 08:10:02 +00:00
fjoe
e4171792ab - Change back "d_ofs" to int8_t to not pessimize padding and size of "struct puc_cfg".
- Use "puc_config_moxa" for Moxa boards that need d_ofs greater than 0x7f

Prodded by:	marcel@, gavin@
MFC after:	3 days
2012-07-31 05:23:23 +00:00
fjoe
2a52af28e6 Remove Moxa CP-132EL definition (RS422/485-only board). 2012-06-21 04:57:59 +00:00
fjoe
490b3d9fc0 Add support for the following Moxa PCIe multiport serial boards:
- CP102E
- CP102EL
- CP132EL
- CP114EL
- CP118EL-A
- CP168EL-A

MFC after:	1 week
2012-06-21 03:10:48 +00:00
jhay
8ab1626704 Add support for the Sunix SER5437A dual serial PCI Express card. 2012-06-08 06:07:23 +00:00
eadler
caff493a8e Add support for Sun 1040 PCI Quad Serial
PR:		kern/163450
Submitted by:	Anonymous Hardware Hacker <silicium@harmony-p.ath.cx>
Approved by:	cperciva
MFC after:	1 week
2012-05-30 03:47:51 +00:00
marius
17e14c6132 - There's no need to overwrite the default device method with the default
one. Interestingly, these are actually the default for quite some time
  (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
  since r52045) but even recently added device drivers do this unnecessarily.
  Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
  Discussed with: jhb
- Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
eadler
7b4ac9ae27 - add support for Titan VScom PCIex-800H
PR:		kern/124128
Submitted by:	Maxim Frolov <maxim.frolov.07@gmail.com> (original)
Approved by:	jhb
MFC after:	1 week
2011-11-15 17:53:29 +00:00
eadler
38110cede2 - add support for CP-104EL-A and CP-104JU to puc
PR:		151365
Submitted by:	Joerg Niendorf <f5d10a@internode.on.net>
Approved by:	jhb
2011-11-11 22:24:16 +00:00
ed
e97eae1577 Mark MALLOC_DEFINEs static that have no corresponding MALLOC_DECLAREs.
This means that their use is restricted to a single C file.
2011-11-07 06:44:47 +00:00
eadler
f22435ed56 - add support for I-O DATA RSA-PCI2/R
PR:		kern/142999
Submitted by:	Takefu Kenji <takefu@airport.fm>
Approved by:	jhb
Approved by:	sahil (mentor)
MFC after:	1 week
2011-10-15 21:06:08 +00:00
ae
8118992bd0 Add Oxford Semiconductor OXPCIe952 (0x1c38) 1 port serial card.
PR:		kern/160895
Submitted by:	Konstantin V. Krotov
MFC after:	1 week
2011-09-29 15:43:02 +00:00
jhb
e2a937e93d Add device id for the Moxa CP-112UL dual-port serial adapters.
Submitted by:	Jan Mikkelsen  janm of transactionware com
Approved by:	re (kib)
MFC after:	1 week
2011-08-15 19:29:25 +00:00
jhb
a11bba2ac0 Add location and pnpinfo strings for puc device ports. The location is
announced during boot and contains the port number.  The pnpinfo string
lists the port type (PUC_TYPE_* constants).

Tested by:	Boris Samorodov  bsam ipt ru
MFC after:	1 week
2011-06-14 18:19:48 +00:00
jhb
d046e38f5f Some style fixes.
Submitted by:	bde
2011-06-06 15:33:15 +00:00
jhb
1075137ca9 - Rename the Cronyx Omega2-PCI entry to Exar XR17C158 since that is the
real owner of the device ID.  Also rename the associated config
  function while here.
- Add support for the 2-port and 4-port Exar parts as well: Exar XR17C/D152
  and Exar XR17C154.

Tested by:	Mike Tancsa, Willy Offermans  Willy of offermans rompen nl
MFC after:	1 week
2011-06-03 20:59:21 +00:00
jhb
a10f288d7e For Timedia multiport serial adapters, the first two ports use a SUN1889
which uses a non-standard clock (* 8) while any additional ports use
SUN1699 chips which use a standard clock.

Tested by:	N.J. Mann   njm of njm me uk
MFC after:	1 week
2011-05-26 20:54:45 +00:00
jhb
76caf7ac52 Add support for the SIIG Cyber 2S PCIe adapter. It is based on an
Oxford Semiconductor OX16PCI954 but uses only two ports with a non-default
clock rate.

PR:		kern/152034
Tested by:	Hans Fiedler  hans of hermes louisville edu
MFC after:	1 week
2011-05-19 11:41:12 +00:00
jhb
6491e2a571 Add an entry for the SIIG Quartet Serial 850 which uses an Oxford
chip with a non-default clock.

PR:		kern/147583
MFC after:	1 week
2011-05-10 12:40:35 +00:00
jhb
6c7b490838 Add an entry for the Kuroutoshikou SERIAL4P-LPPCI2 which uses an Oxford
4 port chip but with a nonstandard clock.

PR:		kern/104212
Submitted by:	Shuichi KITAGUCHI  kit of ysnb net
MFC after:	1 week
2011-05-02 14:34:03 +00:00
jhb
c7e5cfecda Add support for Oxford PCI Express Expresso family devices.
For these devices, the number of supported ports is read from a register
in BAR 0.

PR:		kern/134878
Submitted by:	David Wood  david of wood2 org uk
MFC after:	1 week
2011-04-28 19:19:25 +00:00
emaste
459e9639c3 Add Exar octal PCI UART.
Submitted by:	Mark Johnston
Obtained from:	Sandvine Incorporated
2010-12-18 02:54:51 +00:00
jhb
547182687c Add support for the Perle Speed4 LE.
Submitted by:	Douglas K. Rand  rand of meridian-enviro com
MFC after:	3 days
2010-05-20 13:16:42 +00:00
marcel
2e6099f494 Fix interrupt handling. It started off broken and grew worse over time.
The rewrite of the interrupt handler includes:
o   loop until all pending interrupts are handled. This closes a
    race condition.
o   count the number of interrupt sources we handled so that we can
    properly return FILTER_HANDLED or FILTER_STRAY when we break out
    of the loop.
o   When matching the interrupt source to the devices that have that
    source pending, check only from the set of devices we found to
    have a pending interrupt.

PR:		kern/140947
MFC after:	3 days
2009-12-11 03:08:07 +00:00
marcel
c61e7af92e Add support for the NetMos NM9865 family of Serial/Parallel ports.
Obtained from:	NetMos MCS9865 v1.0.0.1 driver
MFC after:	3 days
2009-12-07 20:05:02 +00:00
np
5bbf1e2151 Make puc(4) aware of this 2 port serial card based on NetMos 9835:
puc0@pci0:4:1:0:       class=0x070002 card=0x00021000 chip=0x98359710 rev=0x01 hdr=0x00

Reviewed by:	marcel@
Approved by:	gnn (mentor)
2009-06-20 00:04:48 +00:00
rwatson
d6cef153cd Add support for the four PUC serial interfaces found on IBM SurePOS 300
series POS terminals.

MFC after:	3 days
Submitted by:	Marc Balmer <marc at msys.ch>
2009-06-02 09:58:17 +00:00
imp
7cf1a35509 remove now-redunant cardbus attachment lines. 2009-03-09 13:25:34 +00:00
jhb
dc03a05b16 Add support for the single-port NetMos NM9835 serial adapter. The puc(4)
entry is a specific entry to override the generic NetMos entry so that
puc(4) will leave this device alone and let uart(4) claim it.

Submitted by:	Navdeep Parhar  nparhar @ gmail
Reviewed by:	marcel
MFC after:	1 week
2009-03-05 16:43:33 +00:00
kevlo
b600a85653 Add support for the Sunix SUN1889-based dual parallel port card.
PR: kern/128219
Submitted by: Thinker K.F. Li <thinker at branda dot to>
2009-02-12 10:39:19 +00:00