59 Commits

Author SHA1 Message Date
jhibbits
00a6946205 Replace the PMC class struct copy with an explicit memcpy()
This should be effectively a nop for all archs, but for some reason the codegen
difference on the PowerPC 970 is such that the struct assignment doesn't work
(unless a printf() using one of the elements in the copied struct follows it),
while the memcpy() succeeds.  On all archs the memcpy() should be expanded to an
inline copy, since the copy is bounded to ~16 bytes.

MFC after:	3 weeks
2018-01-13 04:53:04 +00:00
pfg
260ba0bff1 lib: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 2-Clause license, however the tool I
was using mis-identified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.
2017-11-26 02:00:33 +00:00
kib
3e6224e523 Skylake server core PMC support for hwpmc(4).
Reviewed by:	emaste
Sponsored by:	The FreeBSD Foundation
Hardware provided by:	Intel
MFC after:	2 weeks
Differential revision:	https://reviews.freebsd.org/D12221
2017-09-06 17:19:48 +00:00
kib
054181069c Minor style changes to make forthcoming code stand out less.
Reviewed by:	emaste
Sponsored by:	The FreeBSD Foundation
MFC after:	2 weeks
X-Differential revision:	https://reviews.freebsd.org/D12221
2017-09-06 17:14:23 +00:00
pfg
9e7434b2c5 lib: minor spelling fixes in comments.
No functional change.
2016-05-01 19:37:33 +00:00
rrs
5fd389bc0c Add support for Intel Skylake and Intel Broadwell PMC's. The Broadwell PMC's have been
tested on the Broadwell-Xeon with a hacked up version of pmcstudy -T. I still need
to circle back and add in to pmcstudy all the new tests from the Broadwell Vtune
guide (for the hacked up version I just made it so I could run the -T option). The
Skylake CPU is not yet available (even though Intel is advertising it .. imagine that).
The Skylake PMC's will need to be tested once we can get a sample skylake CPU :-)

Sponsored by: Netflix Inc.
2015-11-30 17:35:49 +00:00
bz
fec51f584e For the Cortex-A8 use the a8 and not the a9 events table.
MFC after:		2 weeks
Sponsored by:		DARPA/AFRL
Differential Revision:	https://reviews.freebsd.org/D3882
2015-10-14 16:56:25 +00:00
br
319e9e4b6c o Rework ARMv7 events list using aliases - same way as we have for arm64.
o Extend it with Cortex A9-specific events.
2015-06-10 12:42:30 +00:00
jhb
d8d8e019c0 Use fixed enum values for PMC_CLASSES().
This removes one of the frequent causes of ABI breakage when new CPU
types are added to hwpmc(4).

Differential Revision:	https://reviews.freebsd.org/D2586
Reviewed by:	davide, emaste, gnn (earlier version)
MFC after:	2 weeks
2015-05-19 18:58:18 +00:00
br
b1f1f07fae Add Performance Monitoring Counters support for AArch64.
Family-common and CPU-specific counters implemented.

Supported CPUs: ARM Cortex A53/57/72.

Reviewed by:	andrew, bz, emaste, gnn, jhb
Sponsored by:	ARM Limited
Differential Revision:	https://reviews.freebsd.org/D2555
2015-05-19 15:25:47 +00:00
jhibbits
2b1ec4f62f Implement hwpmc(4) for Freescale e500 core.
This supports e500v1, e500v2, and e500mc. Tested only on e500v2, but the
performance counters are identical across all, with e500mc having some
additional events.

Relnotes:	Yes
2015-04-18 21:39:17 +00:00
adrian
bc81ea301e Add support for the MIPS74K SoC family performance counters events.
These are similar to the mips24k performance counters - some are
available on perfcnt0/3, some are available on perfcnt1/4.
However, the events aren't all the same.

* Add the events, named the same as from Linux oprofile.
* Verify they're the same as  "MIPS32(R) 74KTM Processor Core Family
  Software User's Manual"; Document Number: MD00519; Revision 01.05.
* Rename INSTRUCTIONS to something else, so it doesn't clash with
  the alias INSTRUCTIONS.  I'll try to tidy this up later; there
  are a few other aliases to add and shuffle around.

Tested:

* QCA9558 SoC (AP135 board) - MIPS74Kc core (no FPU.)
* make universe; where it didn't fail for other reasons.

TODO:

* It'd be nice to support the four performance counters
  in at least this hardware, rather than just two.

Reviewed by:	bsdimp ("looks good; don't break world".)
2015-04-05 02:57:02 +00:00
rstone
94606f7474 Use the correct event table for Haswell Xeon events
Differential Revision:	https://reviews.freebsd.org/D1588
MFC after:	1 month
Sponsored by:	Sandvine Inc.
2015-03-10 01:23:55 +00:00
br
236c1b153d Add ARMv7 performance monitoring counters.
Differential Revision:	https://reviews.freebsd.org/D1687
Reviewed by:	rpaulo
Sponsored by:	DARPA, AFRL
2015-01-28 16:08:07 +00:00
rrs
8bf38c1934 Update the hwpmc driver to have the new type HASWELL_XEON. Also
go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE
to straighten out all the missing PMCs. We also add a new pmc tool
pmcstudy, this allows one to run the various formulas from
the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for
IB/SB and Haswell. The tool also allows one to postulate your own
formulas with any of the various PMC's. At some point I will enahance
this to work with Brendan Gregg's flame-graphs so we can flamegraph
various PMC interactions. Note the manual page also needs some
work (lots of work) but gnn has committed to help me with that ;-)
Reviewed by: gnn
MFC after:1 month
Sponsored by:	Netflix Inc.
2015-01-14 12:46:58 +00:00
kib
23d48b19e1 For Xeon 7500 and 48XX (Nehalem EX and Westmere EX) variants of the
Core i7 and Westmere processors, the uncore PMC subsystem is
completely different from the uncore PMC on smaller versions of CPUs.
Disable existing uncore hwpmc code for EX, otherwise non-existing MSRs
are accessed.

The cores PMCs seems to be identical for non-EX and EX, according to
the SDM.

Reviewed by:	davide, fabient
Sponsored by:	The FreeBSD Foundation
MFC after:	2 weeks
2014-06-04 16:06:38 +00:00
hiren
2babaa36d7 Update hwpmc to support core events for Atom Silvermont microarchitecture.
(Model 0x4D as per Intel document 330061-001 01/2014)

Tested by:	Olivier Cochard-Labbe <olivier@cochatrd.me>
MFC after:	4 weeks
2014-03-20 20:51:08 +00:00
jhibbits
859fb3bb22 Add hwpmc(4) support for the PowerPC 970 class processors, direct events.
This also fixes asserts on removal of the module for the mpc74xx.

The PowerPC 970 processors have two different types of events: direct events
and indirect events.  Thus far only direct events are supported.  I included
some documentation in the driver on how indirect events work, but support is
for the future.

MFC after:	1 month
2014-02-01 02:03:50 +00:00
sbruno
18d941830f Update hwpmc to support Haswell class processors.
0x3C:      /* Per Intel document 325462-045US 01/2013. */

Add manpage to document all the goodness that is available in this
processor model.

Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	jimharris, sbruno
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
2013-03-28 19:15:54 +00:00
sbruno
577b42d393 Update hwpmc to support the Xeon class of Ivybridge processors.
case 0x3E:      /* Per Intel document 325462-045US 01/2013. */

Add manpage to document all the goodness that is available in this
processor model.

No support for uncore events at this time.

Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	davide, jimharris, sbruno
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
2013-01-31 22:09:53 +00:00
dim
9413d82612 Fix a few warnings from newer clang 3.2 in libpmc, about comparing enum
pmc_event values against integer constants which fall outside the enum
range.

Reviewed by:	fabient, sbruno
MFC after:	3 days
2012-11-05 18:49:21 +00:00
sbruno
88f73ca292 Cleanup and rename some variables in libpmc and hwpmc.
Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	jimharris@ sbruno@
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
2012-10-24 01:26:29 +00:00
sbruno
90144fd204 Update hwpmc to support the Xeon class of Sandybridge processors.
(Model 0x2D     /* Per Intel document 253669-044US 08/2012. */)

Add manpage to document all the goodness that is available in this
processor model.

No support for uncore events at this time.

Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	jimharris@ fabient@
Obtained from:	Yahoo! Inc.
MFC after:	  2 weeks
2012-10-19 17:01:27 +00:00
fabient
2a46ae3db5 Add Intel Ivy Bridge support to hwpmc(9).
Update offcore RSP token for Sandy Bridge.
Note: No uncore support.

Will works on Family 6 Model 3a.

MFC after: 1 month
Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
fabient
5edfb77dd3 Add software PMC support.
New kernel events can be added at various location for sampling or counting.
This will for example allow easy system profiling whatever the processor is
with known tools like pmcstat(8).

Simultaneous usage of software PMC and hardware PMC is possible, for example
looking at the lock acquire failure, page fault while sampling on
instructions.

Sponsored by: NETASQ
MFC after:	1 month
2012-03-28 20:58:30 +00:00
gonzo
42ce1eaaa2 Add Octeon-related parts to libpmc 2012-03-23 00:10:21 +00:00
gonzo
aefc71658f Make reusable part of code have mips prefix, not mips24 2012-03-22 18:07:44 +00:00
davide
8636a37ecc - Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events)
- New manpages with event lists.
- Add MSRs for the Intel Sandy Bridge microarchitecture

Reviewed by:	attilio, brueffer, fabient
Approved by:	gnn (mentor)
MFC after:	3 weeks
2012-03-01 21:23:26 +00:00
jhibbits
8eb9e6b548 Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x).
Sampling is in progress.

Approved by:	nwhitehorn (mentor)
MFC after:	9.0-RELEASE
2011-12-24 19:34:52 +00:00
dim
3531846fa5 In lib/libpmc/libpmc.c, struct pmc_cputype_map's pm_cputype field should
be of type 'enum pmc_cputype', not 'enum pmc_class'.

MFC after:	1 week
2011-12-16 00:13:43 +00:00
fabient
c0da433b0a Add a flush of the current PMC log buffer before displaying the next top.
As the underlying block is 4KB if the PMC throughput is low the measurement
will be reported on the next tick. pmcstat(8) use the modified flush API to
reclaim current buffer before displaying next top.

MFC after:	1 month
2011-10-18 15:25:43 +00:00
fabient
dd461c3739 Fix invalid class removal when IAF is not the last class.
Keep IAF class with 0 PMC and change the alias in libpmc to IAP.

MFC after:	1 week
2010-09-05 13:31:14 +00:00
rstone
01a827bd91 When configuring hwpmc to use the EXT_SNOOP event, only send a default cachestate qualifier on the Atom processor. Other Intel processors do not accept a cachestate qualifier and currently hwpmc will return EINVAL if you try to use the EXT_SNOOP event on those processors
Approved by:	jkoshy (mentor)
MFC after:	2 weeks
2010-05-01 21:59:06 +00:00
fabient
85d5b2855f - Support for uncore counting events: one fixed PMC with the uncore
domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
  There is some removed events in the documentation, they have been
  kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.

Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
gnn
acf511e4d0 Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.
Add macros for properly accessing coprocessor 0 registers that
support performance counters.

Reviewed by:	jkoshy rpaulo fabien imp
MFC after:	1 month
2010-03-03 15:05:58 +00:00
jkoshy
63fd65d19b Bug fix: add a missing initializer.
Submitted by:	Luca Pizzamiglio <luca.pizzamiglio at gmail dot com>
PR:		i386/142742
2010-01-12 17:03:55 +00:00
rpaulo
f7db53a9d1 Intel XScale hwpmc(4) support.
This brings hwpmc(4) support for 2nd and 3rd generation XScale cores.
Right now it's enabled by default to make sure we test this a bit.
When the time comes it can be disabled by default.
Tested on Gateworks boards.

A man page is coming.

Obtained from:	//depot/user/rpaulo/xscalepmc/...
2009-12-23 23:16:54 +00:00
jkoshy
befdc81d08 Not all Intel Core (TM) CPUs implement PMC_CLASS_IAF fixed-function
counters.  For such CPUs, use an alternate mapping of convenience
names to events supported by PMC_CLASS_IAP programmable counters.

Testing and review by:	fabient
2009-10-24 04:11:40 +00:00
jkoshy
39e03aaa26 Fix parsing of Core2 event qualifiers.
Submitted by:	Nikola K <laladelausanne at gmail dot com>
2009-06-09 06:34:48 +00:00
jeff
ca96799f52 - Add support for nehalem/corei7 cpus. This supports all of the core
counters defined in the reference manual.  It does not support the
   'uncore' events.

Reviewed by:	jkoshy
Sponsored by:	Nokia
2009-01-27 07:29:37 +00:00
jkoshy
dbaaeca1e6 Fixes for Core2 Extreme support.
Submitted by:	 "Artem Belevich" <artemb at gmail dot com>
2008-12-03 17:30:36 +00:00
jkoshy
aa86a7c59e - Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo
and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and
  model 0x1C (Atom).

  In these CPUs, the actual numbers, kinds and widths of PMCs present
  need to queried at run time.  Support for specific "architectural"
  events also needs to be queried at run time.

  Model 0xE CPUs support programmable PMCs, subsequent CPUs
  additionally support "fixed-function" counters.

- Use event names that are close to vendor documentation, taking in
  account that:
  - events with identical semantics on two or more CPUs in this family
    can have differing names in vendor documentation,
  - identical vendor event names may map to differing events across
    CPUs,
  - each type of CPU supports a different subset of measurable
    events.

  Fixed-function and programmable counters both use the same vendor
  names for events.  The use of a class name prefix ("iaf-" or
  "iap-" respectively) permits these to be distinguished.

- In libpmc, refactor pmc_name_of_event() into a public interface
  and an internal helper function, for use by log handling code.

- Minor code tweaks: staticize a global, freshen a few comments.

Tested by:	gnn
2008-11-27 09:00:47 +00:00
jkoshy
62245b8648 - Sparsely number enumerations 'pmc_cputype' and 'pmc_event' in order to
reduce ABI disruptions when new cpu types and new PMC events are added
  in the future.
- Support alternate spellings for PMC events.  Derive the canonical
  spelling of an event name from its enumeration name in 'enum pmc_event'.
- Provide a way for users to disambiguate between identically named events
  supported by multiple classes of PMCs in a CPU.
- Change libpmc's machine-dependent event specifier parsing code to
  better support CPUs containing two or more classes of PMC resources.
2008-10-09 14:55:45 +00:00
jkoshy
8dda766e41 Whitespace fixes. 2008-09-17 04:13:14 +00:00
jkoshy
5dfb9467b3 Add event name aliases for Pentium PMCs. 2008-09-17 03:53:37 +00:00
jkoshy
f145085b0d Correct an event name alias: event "k7-dc-misses" does not support
a unitmask.
2008-09-16 14:13:03 +00:00
jkoshy
9efc2e038a Bring the behaviour of pmc_capabilities() and pmc_width() in line with
documentation: set 'errno' and return -1 in case of an error.

Update (c) years.
2008-03-12 15:51:32 +00:00
jkoshy
93ff0fa40d Improve style(9) compliance and trim a long text line. 2007-12-07 13:52:51 +00:00
jkoshy
9b08351962 Correct a typo in an event name alias.
Reported by: 	Harald Servat <redcrash at gmail dot com>
2007-04-11 04:52:09 +00:00
jkoshy
9621023f82 Update the pmc(3) manual page's date string and freshen the year in the (c) line for
pmc.3 and libpmc.c.
2006-03-20 15:28:59 +00:00