08aa4c94b8
- Remove double buffering interrupt and isochronous traffic via the transaction translator. It can be avoided because the DWC OTG will always delay the start split transactions for interrupt and isochronous traffic, but will not delay the complete split transactions, if we set the odd frame bit correctly. - Need to check the transfer cache field in the device done function to be sure all allocated channels are freed and not the transfer first one. This seems to resolve the control endpoint transfer type quirk which is now removed. - Make sure any received data upon TX is dumped else RX path will stop. - Transmit isochronous data before receiving isochronous data as a means to optimise the TT schedule. - Implement a simple TT bandwidth scheduler. - Cleanup use of old "td->error" variable. - On interrupt IN traffic via the transaction translator we simply ignore missed transfer opportunities and silently retry the transaction upon next available time slot. MFC after: 3 days |
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at91dci_atmelarm.c | ||
at91dci_fdt.c | ||
at91dci.c | ||
at91dci.h | ||
atmegadci_atmelarm.c | ||
atmegadci.c | ||
atmegadci.h | ||
avr32dci.c | ||
avr32dci.h | ||
dwc_otg_fdt.c | ||
dwc_otg.c | ||
dwc_otg.h | ||
dwc_otgreg.h | ||
ehci_fsl.c | ||
ehci_imx.c | ||
ehci_ixp4xx.c | ||
ehci_mv.c | ||
ehci_pci.c | ||
ehci.c | ||
ehci.h | ||
ehcireg.h | ||
musb_otg_atmelarm.c | ||
musb_otg.c | ||
musb_otg.h | ||
ohci_atmelarm.c | ||
ohci_fdt.c | ||
ohci_pci.c | ||
ohci_s3c24x0.c | ||
ohci.c | ||
ohci.h | ||
ohcireg.h | ||
saf1761_otg_boot.c | ||
saf1761_otg_fdt.c | ||
saf1761_otg_reg.h | ||
saf1761_otg.c | ||
saf1761_otg.h | ||
uhci_pci.c | ||
uhci.c | ||
uhci.h | ||
uhcireg.h | ||
usb_controller.c | ||
uss820dci_atmelarm.c | ||
uss820dci.c | ||
uss820dci.h | ||
xhci_pci.c | ||
xhci.c | ||
xhci.h | ||
xhcireg.h |