356 lines
11 KiB
C
356 lines
11 KiB
C
/*-
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* Copyright (C) 2009-2011 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_CESA_H_
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#define _DEV_CESA_H_
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/* Maximum number of allocated sessions */
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#define CESA_SESSIONS 64
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/* Maximum number of queued requests */
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#define CESA_REQUESTS 256
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/*
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* CESA is able to process data only in CESA SRAM, which is quite small (2 kB).
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* We have to fit a packet there, which contains SA descriptor, keys, IV
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* and data to be processed. Every request must be converted into chain of
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* packets and each packet can hold about 1.75 kB of data.
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*
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* To process each packet we need at least 1 SA descriptor and at least 4 TDMA
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* descriptors. However there are cases when we use 2 SA and 8 TDMA descriptors
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* per packet. Number of used TDMA descriptors can increase beyond given values
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* if data in the request is fragmented in physical memory.
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*
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* The driver uses preallocated SA and TDMA descriptors pools to get best
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* performace. Size of these pools should match expected request size. Example:
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*
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* Expected average request size: 1.5 kB (Ethernet MTU)
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* Packets per average request: (1.5 kB / 1.75 kB) = 1
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* SA decriptors per average request (worst case): 1 * 2 = 2
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* TDMA desctiptors per average request (worst case): 1 * 8 = 8
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*
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* More TDMA descriptors should be allocated, if data fragmentation is expected
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* (for example while processing mbufs larger than MCLBYTES). The driver may use
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* 2 additional TDMA descriptors per each discontinuity in the physical data
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* layout.
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*/
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/* Values below are optimized for requests containing about 1.5 kB of data */
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#define CESA_SA_DESC_PER_REQ 2
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#define CESA_TDMA_DESC_PER_REQ 8
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#define CESA_SA_DESCRIPTORS (CESA_SA_DESC_PER_REQ * CESA_REQUESTS)
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#define CESA_TDMA_DESCRIPTORS (CESA_TDMA_DESC_PER_REQ * CESA_REQUESTS)
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/* Useful constants */
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#define CESA_HMAC_HASH_LENGTH 12
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#define CESA_MAX_FRAGMENTS 64
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#define CESA_SRAM_SIZE 2048
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/*
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* CESA_MAX_HASH_LEN is maximum length of hash generated by CESA.
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* As CESA suports only MD5 and SHA1 this equals to 20 bytes.
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* However we increase the value to 24 bytes to meet alignment
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* requirements in cesa_sa_data structure.
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*/
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#define CESA_MAX_HASH_LEN 24
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#define CESA_MAX_KEY_LEN 32
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#define CESA_MAX_IV_LEN 16
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#define CESA_MAX_HMAC_BLOCK_LEN 64
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#define CESA_MAX_MKEY_LEN CESA_MAX_HMAC_BLOCK_LEN
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#define CESA_MAX_PACKET_SIZE (CESA_SRAM_SIZE - CESA_DATA(0))
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#define CESA_MAX_REQUEST_SIZE 65535
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/* Locking macros */
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#define CESA_LOCK(sc, what) mtx_lock(&(sc)->sc_ ## what ## _lock)
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#define CESA_UNLOCK(sc, what) mtx_unlock(&(sc)->sc_ ## what ## _lock)
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#define CESA_LOCK_ASSERT(sc, what) \
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mtx_assert(&(sc)->sc_ ## what ## _lock, MA_OWNED)
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/* Registers read/write macros */
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#define CESA_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define CESA_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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/* Generic allocator for objects */
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#define CESA_GENERIC_ALLOC_LOCKED(sc, obj, pool) do { \
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CESA_LOCK(sc, pool); \
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\
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if (STAILQ_EMPTY(&(sc)->sc_free_ ## pool)) \
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obj = NULL; \
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else { \
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obj = STAILQ_FIRST(&(sc)->sc_free_ ## pool); \
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STAILQ_REMOVE_HEAD(&(sc)->sc_free_ ## pool, \
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obj ## _stq); \
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} \
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\
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CESA_UNLOCK(sc, pool); \
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} while (0)
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#define CESA_GENERIC_FREE_LOCKED(sc, obj, pool) do { \
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CESA_LOCK(sc, pool); \
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STAILQ_INSERT_TAIL(&(sc)->sc_free_ ## pool, obj, \
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obj ## _stq); \
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CESA_UNLOCK(sc, pool); \
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} while (0)
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/* CESA SRAM offset calculation macros */
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#define CESA_SA_DATA(member) \
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(sizeof(struct cesa_sa_hdesc) + offsetof(struct cesa_sa_data, member))
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#define CESA_DATA(offset) \
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(sizeof(struct cesa_sa_hdesc) + sizeof(struct cesa_sa_data) + offset)
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struct cesa_tdma_hdesc {
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uint16_t cthd_byte_count;
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uint16_t cthd_flags;
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uint32_t cthd_src;
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uint32_t cthd_dst;
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uint32_t cthd_next;
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};
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struct cesa_sa_hdesc {
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uint32_t cshd_config;
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uint16_t cshd_enc_src;
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uint16_t cshd_enc_dst;
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uint32_t cshd_enc_dlen;
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uint32_t cshd_enc_key;
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uint16_t cshd_enc_iv;
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uint16_t cshd_enc_iv_buf;
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uint16_t cshd_mac_src;
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uint16_t cshd_mac_total_dlen;
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uint16_t cshd_mac_dst;
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uint16_t cshd_mac_dlen;
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uint16_t cshd_mac_iv_in;
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uint16_t cshd_mac_iv_out;
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};
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struct cesa_sa_data {
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uint8_t csd_key[CESA_MAX_KEY_LEN];
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uint8_t csd_iv[CESA_MAX_IV_LEN];
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uint8_t csd_hiv_in[CESA_MAX_HASH_LEN];
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uint8_t csd_hiv_out[CESA_MAX_HASH_LEN];
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uint8_t csd_hash[CESA_MAX_HASH_LEN];
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};
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struct cesa_dma_mem {
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void *cdm_vaddr;
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bus_addr_t cdm_paddr;
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bus_dma_tag_t cdm_tag;
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bus_dmamap_t cdm_map;
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};
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struct cesa_tdma_desc {
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struct cesa_tdma_hdesc *ctd_cthd;
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bus_addr_t ctd_cthd_paddr;
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STAILQ_ENTRY(cesa_tdma_desc) ctd_stq;
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};
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struct cesa_sa_desc {
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struct cesa_sa_hdesc *csd_cshd;
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bus_addr_t csd_cshd_paddr;
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STAILQ_ENTRY(cesa_sa_desc) csd_stq;
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};
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struct cesa_session {
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uint32_t cs_sid;
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uint32_t cs_config;
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unsigned int cs_klen;
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unsigned int cs_ivlen;
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unsigned int cs_hlen;
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unsigned int cs_mblen;
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uint8_t cs_key[CESA_MAX_KEY_LEN];
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uint8_t cs_aes_dkey[CESA_MAX_KEY_LEN];
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uint8_t cs_hiv_in[CESA_MAX_HASH_LEN];
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uint8_t cs_hiv_out[CESA_MAX_HASH_LEN];
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STAILQ_ENTRY(cesa_session) cs_stq;
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};
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struct cesa_request {
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struct cesa_sa_data *cr_csd;
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bus_addr_t cr_csd_paddr;
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struct cryptop *cr_crp;
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struct cryptodesc *cr_enc;
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struct cryptodesc *cr_mac;
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struct cesa_session *cr_cs;
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bus_dmamap_t cr_dmap;
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int cr_dmap_loaded;
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STAILQ_HEAD(, cesa_tdma_desc) cr_tdesc;
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STAILQ_HEAD(, cesa_sa_desc) cr_sdesc;
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STAILQ_ENTRY(cesa_request) cr_stq;
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};
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struct cesa_packet {
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STAILQ_HEAD(, cesa_tdma_desc) cp_copyin;
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STAILQ_HEAD(, cesa_tdma_desc) cp_copyout;
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unsigned int cp_size;
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unsigned int cp_offset;
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};
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struct cesa_softc {
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device_t sc_dev;
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int32_t sc_cid;
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struct resource *sc_res[2];
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void *sc_icookie;
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bus_dma_tag_t sc_data_dtag;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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int sc_error;
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int sc_tperr;
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struct mtx sc_sc_lock;
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int sc_blocked;
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/* TDMA descriptors pool */
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struct mtx sc_tdesc_lock;
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struct cesa_tdma_desc sc_tdesc[CESA_TDMA_DESCRIPTORS];
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struct cesa_dma_mem sc_tdesc_cdm;
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STAILQ_HEAD(, cesa_tdma_desc) sc_free_tdesc;
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/* SA descriptors pool */
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struct mtx sc_sdesc_lock;
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struct cesa_sa_desc sc_sdesc[CESA_SA_DESCRIPTORS];
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struct cesa_dma_mem sc_sdesc_cdm;
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STAILQ_HEAD(, cesa_sa_desc) sc_free_sdesc;
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/* Requests pool */
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struct mtx sc_requests_lock;
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struct cesa_request sc_requests[CESA_REQUESTS];
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struct cesa_dma_mem sc_requests_cdm;
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STAILQ_HEAD(, cesa_request) sc_free_requests;
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STAILQ_HEAD(, cesa_request) sc_ready_requests;
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STAILQ_HEAD(, cesa_request) sc_queued_requests;
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/* Sessions pool */
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struct mtx sc_sessions_lock;
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struct cesa_session sc_sessions[CESA_SESSIONS];
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STAILQ_HEAD(, cesa_session) sc_free_sessions;
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/* CESA SRAM Address */
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bus_addr_t sc_sram_base;
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};
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struct cesa_chain_info {
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struct cesa_softc *cci_sc;
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struct cesa_request *cci_cr;
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struct cryptodesc *cci_enc;
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struct cryptodesc *cci_mac;
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uint32_t cci_config;
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int cci_error;
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};
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/* CESA descriptors flags definitions */
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#define CESA_CTHD_OWNED (1 << 15)
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#define CESA_CSHD_MAC (0 << 0)
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#define CESA_CSHD_ENC (1 << 0)
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#define CESA_CSHD_MAC_AND_ENC (2 << 0)
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#define CESA_CSHD_ENC_AND_MAC (3 << 0)
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#define CESA_CSHD_OP_MASK (3 << 0)
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#define CESA_CSHD_MD5 (4 << 4)
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#define CESA_CSHD_SHA1 (5 << 4)
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#define CESA_CSHD_MD5_HMAC ((6 << 4) | (1 << 7))
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#define CESA_CSHD_SHA1_HMAC ((7 << 4) | (1 << 7))
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#define CESA_CSHD_DES (1 << 8)
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#define CESA_CSHD_3DES (2 << 8)
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#define CESA_CSHD_AES (3 << 8)
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#define CESA_CSHD_DECRYPT (1 << 12)
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#define CESA_CSHD_CBC (1 << 16)
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#define CESA_CSHD_3DES_EDE (1 << 20)
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#define CESA_CSH_AES_KLEN_128 (0 << 24)
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#define CESA_CSH_AES_KLEN_192 (1 << 24)
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#define CESA_CSH_AES_KLEN_256 (2 << 24)
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#define CESA_CSH_AES_KLEN_MASK (3 << 24)
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#define CESA_CSHD_FRAG_FIRST (1 << 30)
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#define CESA_CSHD_FRAG_LAST (2U << 30)
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#define CESA_CSHD_FRAG_MIDDLE (3U << 30)
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/* CESA registers definitions */
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#define CESA_ICR 0xDE20
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#define CESA_ICR_ACCTDMA (1 << 7)
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#define CESA_ICR_TPERR (1 << 12)
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#define CESA_ICM 0xDE24
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#define CESA_ICM_ACCTDMA CESA_ICR_ACCTDMA
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#define CESA_ICM_TPERR CESA_ICR_TPERR
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/* CESA TDMA registers definitions */
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#define CESA_TDMA_ND 0x0830
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#define CESA_TDMA_CR 0x0840
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#define CESA_TDMA_CR_DBL128 (4 << 0)
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#define CESA_TDMA_CR_ORDEN (1 << 4)
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#define CESA_TDMA_CR_SBL128 (4 << 6)
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#define CESA_TDMA_CR_NBS (1 << 11)
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#define CESA_TDMA_CR_ENABLE (1 << 12)
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#define CESA_TDMA_CR_FETCHND (1 << 13)
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#define CESA_TDMA_CR_ACTIVE (1 << 14)
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#define CESA_TDMA_ECR 0x08C8
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#define CESA_TDMA_ECR_MISS (1 << 0)
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#define CESA_TDMA_ECR_DOUBLE_HIT (1 << 1)
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#define CESA_TDMA_ECR_BOTH_HIT (1 << 2)
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#define CESA_TDMA_ECR_DATA_ERROR (1 << 3)
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#define CESA_TDMA_EMR 0x08CC
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#define CESA_TDMA_EMR_MISS CESA_TDMA_ECR_MISS
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#define CESA_TDMA_EMR_DOUBLE_HIT CESA_TDMA_ECR_DOUBLE_HIT
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#define CESA_TDMA_EMR_BOTH_HIT CESA_TDMA_ECR_BOTH_HIT
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#define CESA_TDMA_EMR_DATA_ERROR CESA_TDMA_ECR_DATA_ERROR
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/* CESA TDMA address decoding registers */
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#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xA04)
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#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xA00)
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#define MV_WIN_CESA_MAX 4
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/* CESA SA registers definitions */
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#define CESA_SA_CMD 0xDE00
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#define CESA_SA_CMD_ACTVATE (1 << 0)
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#define CESA_SA_DPR 0xDE04
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#define CESA_SA_CR 0xDE08
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#define CESA_SA_CR_WAIT_FOR_TDMA (1 << 7)
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#define CESA_SA_CR_ACTIVATE_TDMA (1 << 9)
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#define CESA_SA_CR_MULTI_MODE (1 << 11)
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#define CESA_SA_SR 0xDE0C
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#define CESA_SA_SR_ACTIVE (1 << 0)
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#endif
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