aff98f17c6
rate support, disable it.
48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/*
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* Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd
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* Copyright (c) 2010 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ar5416/ar5416.h"
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#include "ar5416/ar5416reg.h"
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#include "ar5416/ar5416phy.h"
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#include "ar9001/ar9130_phy.h"
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void
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ar9130InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan)
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{
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uint32_t pll;
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/*
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* XXX TODO: support half/quarter rates
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*/
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if (chan && IEEE80211_IS_CHAN_5GHZ(chan))
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pll = 0x1450;
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else
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pll = 0x1458;
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OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
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OS_DELAY(RTC_PLL_SETTLE_DELAY);
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OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK);
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}
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