8bf1194fe5
Freescale's QorIQ line includes a new ethernet controller, based on their Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame manager, Buffer manager, and Queue manager to improve performance across all interfaces by being able to pass data directly between hardware acceleration interfaces. As part of this import, Freescale's Netcomm Software (ncsw) driver is imported. This was an attempt by Freescale to create an OS-agnostic sub-driver for managing the hardware, using shims to interface to the OS-specific APIs. This work was abandoned, and Freescale's primary work is in the Linux driver (dual BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than going through the vendor area. Going forward, FreeBSD-specific changes may be made to the ncsw code, diverging from the upstream in potentially incompatible ways. An alternative could be to import the Linux driver itself, using the linuxKPI layer, as that would maintain parity with the vendor-maintained driver. However, the Linux driver has not been evaluated for reliability yet, and may have issues with the import, whereas the ncsw-based driver in this commit was completed by Semihalf 4 years ago, and is very stable. Other SoC modules based on DPAA, which could be added in the future: * Security and Encryption engine (SEC4.x, SEC5.x) * RAID engine Additional work to be done: * Implement polling mode * Test vlan support * Add support for the Pattern Matching Engine, which can do regular expression matching on packets. This driver has been tested on the P5020 QorIQ SoC. Others listed in the dtsec(4) manual page are expected to work as the same DPAA engine is included in all. Obtained from: Semihalf Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing
880 lines
19 KiB
C
880 lines
19 KiB
C
/*-
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* Copyright (c) 2011-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <sys/sysctl.h>
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#include <sys/sockio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <net/if_arp.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/openfirm.h>
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#include "miibus_if.h"
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#include <contrib/ncsw/inc/Peripherals/fm_mac_ext.h>
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#include <contrib/ncsw/inc/Peripherals/fm_port_ext.h>
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#include <contrib/ncsw/inc/xx_ext.h>
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#include "fman.h"
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#include "if_dtsec.h"
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#include "if_dtsec_im.h"
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#include "if_dtsec_rm.h"
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/**
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* @group dTSEC private defines.
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* @{
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*/
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/**
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* dTSEC FMan MAC exceptions info struct.
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*/
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struct dtsec_fm_mac_ex_str {
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const int num;
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const char *str;
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};
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/* XXX: Handle to FM_MAC instance of dTSEC0 */
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/* From QorIQ Data Path Acceleration Architecture Reference Manual, Rev 2, page
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* 3-37, "The MII management hardware is shared by all dTSECs... only through
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* the MIIM registers of dTSEC1 can external PHY's be accessed and configured."
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*/
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static t_Handle dtsec_mdio_mac_handle;
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/** @} */
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/**
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* @group FMan MAC routines.
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* @{
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*/
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#define DTSEC_MAC_EXCEPTIONS_END (-1)
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/**
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* FMan MAC exceptions.
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*/
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static const struct dtsec_fm_mac_ex_str dtsec_fm_mac_exceptions[] = {
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{ e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO, "MDIO scan event" },
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{ e_FM_MAC_EX_10G_MDIO_CMD_CMPL, "MDIO command completion" },
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{ e_FM_MAC_EX_10G_REM_FAULT, "Remote fault" },
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{ e_FM_MAC_EX_10G_LOC_FAULT, "Local fault" },
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{ e_FM_MAC_EX_10G_1TX_ECC_ER, "Transmit frame ECC error" },
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{ e_FM_MAC_EX_10G_TX_FIFO_UNFL, "Transmit FIFO underflow" },
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{ e_FM_MAC_EX_10G_TX_FIFO_OVFL, "Receive FIFO overflow" },
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{ e_FM_MAC_EX_10G_TX_ER, "Transmit frame error" },
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{ e_FM_MAC_EX_10G_RX_FIFO_OVFL, "Receive FIFO overflow" },
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{ e_FM_MAC_EX_10G_RX_ECC_ER, "Receive frame ECC error" },
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{ e_FM_MAC_EX_10G_RX_JAB_FRM, "Receive jabber frame" },
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{ e_FM_MAC_EX_10G_RX_OVRSZ_FRM, "Receive oversized frame" },
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{ e_FM_MAC_EX_10G_RX_RUNT_FRM, "Receive runt frame" },
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{ e_FM_MAC_EX_10G_RX_FRAG_FRM, "Receive fragment frame" },
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{ e_FM_MAC_EX_10G_RX_LEN_ER, "Receive payload length error" },
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{ e_FM_MAC_EX_10G_RX_CRC_ER, "Receive CRC error" },
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{ e_FM_MAC_EX_10G_RX_ALIGN_ER, "Receive alignment error" },
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{ e_FM_MAC_EX_1G_BAB_RX, "Babbling receive error" },
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{ e_FM_MAC_EX_1G_RX_CTL, "Receive control (pause frame) interrupt" },
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{ e_FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET, "Graceful transmit stop "
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"complete" },
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{ e_FM_MAC_EX_1G_BAB_TX, "Babbling transmit error" },
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{ e_FM_MAC_EX_1G_TX_CTL, "Transmit control (pause frame) interrupt" },
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{ e_FM_MAC_EX_1G_TX_ERR, "Transmit error" },
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{ e_FM_MAC_EX_1G_LATE_COL, "Late collision" },
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{ e_FM_MAC_EX_1G_COL_RET_LMT, "Collision retry limit" },
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{ e_FM_MAC_EX_1G_TX_FIFO_UNDRN, "Transmit FIFO underrun" },
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{ e_FM_MAC_EX_1G_MAG_PCKT, "Magic Packet detected when dTSEC is in "
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"Magic Packet detection mode" },
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{ e_FM_MAC_EX_1G_MII_MNG_RD_COMPLET, "MII management read completion" },
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{ e_FM_MAC_EX_1G_MII_MNG_WR_COMPLET, "MII management write completion" },
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{ e_FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET, "Graceful receive stop "
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"complete" },
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{ e_FM_MAC_EX_1G_TX_DATA_ERR, "Internal data error on transmit" },
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{ e_FM_MAC_EX_1G_RX_DATA_ERR, "Internal data error on receive" },
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{ e_FM_MAC_EX_1G_1588_TS_RX_ERR, "Time-Stamp Receive Error" },
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{ e_FM_MAC_EX_1G_RX_MIB_CNT_OVFL, "MIB counter overflow" },
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{ DTSEC_MAC_EXCEPTIONS_END, "" }
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};
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static const char *
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dtsec_fm_mac_ex_to_str(e_FmMacExceptions exception)
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{
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int i;
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for (i = 0; dtsec_fm_mac_exceptions[i].num != exception &&
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dtsec_fm_mac_exceptions[i].num != DTSEC_MAC_EXCEPTIONS_END; ++i)
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;
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if (dtsec_fm_mac_exceptions[i].num == DTSEC_MAC_EXCEPTIONS_END)
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return ("<Unknown Exception>");
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return (dtsec_fm_mac_exceptions[i].str);
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}
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static void
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dtsec_fm_mac_mdio_event_callback(t_Handle h_App,
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e_FmMacExceptions exception)
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{
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struct dtsec_softc *sc;
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sc = h_App;
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device_printf(sc->sc_dev, "MDIO event %i: %s.\n", exception,
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dtsec_fm_mac_ex_to_str(exception));
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}
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static void
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dtsec_fm_mac_exception_callback(t_Handle app, e_FmMacExceptions exception)
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{
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struct dtsec_softc *sc;
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sc = app;
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device_printf(sc->sc_dev, "MAC exception %i: %s.\n", exception,
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dtsec_fm_mac_ex_to_str(exception));
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}
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static void
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dtsec_fm_mac_free(struct dtsec_softc *sc)
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{
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if (sc->sc_mach == NULL)
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return;
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FM_MAC_Disable(sc->sc_mach, e_COMM_MODE_RX_AND_TX);
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FM_MAC_Free(sc->sc_mach);
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sc->sc_mach = NULL;
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}
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static int
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dtsec_fm_mac_init(struct dtsec_softc *sc, uint8_t *mac)
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{
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t_FmMacParams params;
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t_Error error;
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memset(¶ms, 0, sizeof(params));
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memcpy(¶ms.addr, mac, sizeof(params.addr));
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params.baseAddr = sc->sc_fm_base + sc->sc_mac_mem_offset;
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params.enetMode = sc->sc_mac_enet_mode;
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params.macId = sc->sc_eth_id;
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params.mdioIrq = sc->sc_mac_mdio_irq;
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params.f_Event = dtsec_fm_mac_mdio_event_callback;
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params.f_Exception = dtsec_fm_mac_exception_callback;
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params.h_App = sc;
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params.h_Fm = sc->sc_fmh;
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sc->sc_mach = FM_MAC_Config(¶ms);
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if (sc->sc_hidden)
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return (0);
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if (sc->sc_mach == NULL) {
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device_printf(sc->sc_dev, "couldn't configure FM_MAC module.\n"
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);
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return (ENXIO);
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}
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error = FM_MAC_ConfigResetOnInit(sc->sc_mach, TRUE);
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if (error != E_OK) {
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device_printf(sc->sc_dev, "couldn't enable reset on init "
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"feature.\n");
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dtsec_fm_mac_free(sc);
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return (ENXIO);
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}
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/* Do not inform about pause frames */
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error = FM_MAC_ConfigException(sc->sc_mach, e_FM_MAC_EX_1G_RX_CTL,
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FALSE);
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if (error != E_OK) {
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device_printf(sc->sc_dev, "couldn't disable pause frames "
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"exception.\n");
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dtsec_fm_mac_free(sc);
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return (ENXIO);
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}
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error = FM_MAC_Init(sc->sc_mach);
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if (error != E_OK) {
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device_printf(sc->sc_dev, "couldn't initialize FM_MAC module."
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"\n");
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dtsec_fm_mac_free(sc);
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return (ENXIO);
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}
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return (0);
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}
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/** @} */
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/**
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* @group FMan PORT routines.
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* @{
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*/
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static const char *
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dtsec_fm_port_ex_to_str(e_FmPortExceptions exception)
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{
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switch (exception) {
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case e_FM_PORT_EXCEPTION_IM_BUSY:
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return ("IM: RX busy");
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default:
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return ("<Unknown Exception>");
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}
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}
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void
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dtsec_fm_port_rx_exception_callback(t_Handle app,
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e_FmPortExceptions exception)
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{
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struct dtsec_softc *sc;
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sc = app;
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device_printf(sc->sc_dev, "RX exception: %i: %s.\n", exception,
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dtsec_fm_port_ex_to_str(exception));
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}
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void
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dtsec_fm_port_tx_exception_callback(t_Handle app,
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e_FmPortExceptions exception)
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{
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struct dtsec_softc *sc;
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sc = app;
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device_printf(sc->sc_dev, "TX exception: %i: %s.\n", exception,
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dtsec_fm_port_ex_to_str(exception));
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}
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e_FmPortType
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dtsec_fm_port_rx_type(enum eth_dev_type type)
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{
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switch (type) {
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case ETH_DTSEC:
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return (e_FM_PORT_TYPE_RX);
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case ETH_10GSEC:
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return (e_FM_PORT_TYPE_RX_10G);
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default:
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return (e_FM_PORT_TYPE_DUMMY);
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}
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}
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e_FmPortType
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dtsec_fm_port_tx_type(enum eth_dev_type type)
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{
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switch (type) {
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case ETH_DTSEC:
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return (e_FM_PORT_TYPE_TX);
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case ETH_10GSEC:
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return (e_FM_PORT_TYPE_TX_10G);
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default:
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return (e_FM_PORT_TYPE_DUMMY);
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}
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}
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static void
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dtsec_fm_port_free_both(struct dtsec_softc *sc)
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{
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if (sc->sc_rxph) {
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FM_PORT_Free(sc->sc_rxph);
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sc->sc_rxph = NULL;
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}
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if (sc->sc_txph) {
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FM_PORT_Free(sc->sc_txph);
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sc->sc_txph = NULL;
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}
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}
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/** @} */
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/**
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* @group IFnet routines.
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* @{
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*/
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static int
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dtsec_if_enable_locked(struct dtsec_softc *sc)
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{
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int error;
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DTSEC_LOCK_ASSERT(sc);
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error = FM_MAC_Enable(sc->sc_mach, e_COMM_MODE_RX_AND_TX);
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if (error != E_OK)
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return (EIO);
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error = FM_PORT_Enable(sc->sc_rxph);
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if (error != E_OK)
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return (EIO);
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error = FM_PORT_Enable(sc->sc_txph);
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if (error != E_OK)
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return (EIO);
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sc->sc_ifnet->if_drv_flags |= IFF_DRV_RUNNING;
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/* Refresh link state */
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dtsec_miibus_statchg(sc->sc_dev);
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return (0);
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}
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static int
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dtsec_if_disable_locked(struct dtsec_softc *sc)
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{
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int error;
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DTSEC_LOCK_ASSERT(sc);
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error = FM_MAC_Disable(sc->sc_mach, e_COMM_MODE_RX_AND_TX);
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if (error != E_OK)
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return (EIO);
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error = FM_PORT_Disable(sc->sc_rxph);
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if (error != E_OK)
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return (EIO);
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error = FM_PORT_Disable(sc->sc_txph);
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if (error != E_OK)
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return (EIO);
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sc->sc_ifnet->if_drv_flags &= ~IFF_DRV_RUNNING;
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return (0);
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}
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static int
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dtsec_if_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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{
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struct dtsec_softc *sc;
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struct ifreq *ifr;
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int error;
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sc = ifp->if_softc;
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ifr = (struct ifreq *)data;
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error = 0;
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/* Basic functionality to achieve media status reports */
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switch (command) {
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case SIOCSIFFLAGS:
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DTSEC_LOCK(sc);
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if (sc->sc_ifnet->if_flags & IFF_UP)
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error = dtsec_if_enable_locked(sc);
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else
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error = dtsec_if_disable_locked(sc);
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DTSEC_UNLOCK(sc);
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break;
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case SIOCGIFMEDIA:
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case SIOCSIFMEDIA:
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error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media,
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command);
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break;
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default:
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error = ether_ioctl(ifp, command, data);
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}
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return (error);
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}
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static void
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dtsec_if_tick(void *arg)
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{
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struct dtsec_softc *sc;
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sc = arg;
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/* TODO */
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DTSEC_LOCK(sc);
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mii_tick(sc->sc_mii);
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callout_reset(&sc->sc_tick_callout, hz, dtsec_if_tick, sc);
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DTSEC_UNLOCK(sc);
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}
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static void
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dtsec_if_deinit_locked(struct dtsec_softc *sc)
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{
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DTSEC_LOCK_ASSERT(sc);
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DTSEC_UNLOCK(sc);
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callout_drain(&sc->sc_tick_callout);
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DTSEC_LOCK(sc);
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}
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static void
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dtsec_if_init_locked(struct dtsec_softc *sc)
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{
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int error;
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DTSEC_LOCK_ASSERT(sc);
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/* Set MAC address */
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error = FM_MAC_ModifyMacAddr(sc->sc_mach,
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(t_EnetAddr *)IF_LLADDR(sc->sc_ifnet));
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if (error != E_OK) {
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device_printf(sc->sc_dev, "couldn't set MAC address.\n");
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goto err;
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}
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/* Start MII polling */
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if (sc->sc_mii)
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callout_reset(&sc->sc_tick_callout, hz, dtsec_if_tick, sc);
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if (sc->sc_ifnet->if_flags & IFF_UP) {
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error = dtsec_if_enable_locked(sc);
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if (error != 0)
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goto err;
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} else {
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|
error = dtsec_if_disable_locked(sc);
|
|
if (error != 0)
|
|
goto err;
|
|
}
|
|
|
|
return;
|
|
|
|
err:
|
|
dtsec_if_deinit_locked(sc);
|
|
device_printf(sc->sc_dev, "initialization error.\n");
|
|
return;
|
|
}
|
|
|
|
static void
|
|
dtsec_if_init(void *data)
|
|
{
|
|
struct dtsec_softc *sc;
|
|
|
|
sc = data;
|
|
|
|
DTSEC_LOCK(sc);
|
|
dtsec_if_init_locked(sc);
|
|
DTSEC_UNLOCK(sc);
|
|
}
|
|
|
|
static void
|
|
dtsec_if_start(struct ifnet *ifp)
|
|
{
|
|
struct dtsec_softc *sc;
|
|
|
|
sc = ifp->if_softc;
|
|
DTSEC_LOCK(sc);
|
|
sc->sc_start_locked(sc);
|
|
DTSEC_UNLOCK(sc);
|
|
}
|
|
|
|
static void
|
|
dtsec_if_watchdog(struct ifnet *ifp)
|
|
{
|
|
/* TODO */
|
|
}
|
|
/** @} */
|
|
|
|
|
|
/**
|
|
* @group IFmedia routines.
|
|
* @{
|
|
*/
|
|
static int
|
|
dtsec_ifmedia_upd(struct ifnet *ifp)
|
|
{
|
|
struct dtsec_softc *sc = ifp->if_softc;
|
|
|
|
DTSEC_LOCK(sc);
|
|
mii_mediachg(sc->sc_mii);
|
|
DTSEC_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
dtsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
|
|
{
|
|
struct dtsec_softc *sc = ifp->if_softc;
|
|
|
|
DTSEC_LOCK(sc);
|
|
|
|
mii_pollstat(sc->sc_mii);
|
|
|
|
ifmr->ifm_active = sc->sc_mii->mii_media_active;
|
|
ifmr->ifm_status = sc->sc_mii->mii_media_status;
|
|
|
|
DTSEC_UNLOCK(sc);
|
|
}
|
|
/** @} */
|
|
|
|
|
|
/**
|
|
* @group dTSEC bus interface.
|
|
* @{
|
|
*/
|
|
static void
|
|
dtsec_configure_mode(struct dtsec_softc *sc)
|
|
{
|
|
char tunable[64];
|
|
|
|
snprintf(tunable, sizeof(tunable), "%s.independent_mode",
|
|
device_get_nameunit(sc->sc_dev));
|
|
|
|
sc->sc_mode = DTSEC_MODE_REGULAR;
|
|
TUNABLE_INT_FETCH(tunable, &sc->sc_mode);
|
|
|
|
if (sc->sc_mode == DTSEC_MODE_REGULAR) {
|
|
sc->sc_port_rx_init = dtsec_rm_fm_port_rx_init;
|
|
sc->sc_port_tx_init = dtsec_rm_fm_port_tx_init;
|
|
sc->sc_start_locked = dtsec_rm_if_start_locked;
|
|
} else {
|
|
sc->sc_port_rx_init = dtsec_im_fm_port_rx_init;
|
|
sc->sc_port_tx_init = dtsec_im_fm_port_tx_init;
|
|
sc->sc_start_locked = dtsec_im_if_start_locked;
|
|
}
|
|
|
|
device_printf(sc->sc_dev, "Configured for %s mode.\n",
|
|
(sc->sc_mode == DTSEC_MODE_REGULAR) ? "regular" : "independent");
|
|
}
|
|
|
|
int
|
|
dtsec_attach(device_t dev)
|
|
{
|
|
struct dtsec_softc *sc;
|
|
int error;
|
|
struct ifnet *ifp;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
sc->sc_dev = dev;
|
|
sc->sc_mac_mdio_irq = NO_IRQ;
|
|
sc->sc_eth_id = device_get_unit(dev);
|
|
|
|
|
|
/* Check if MallocSmart allocator is ready */
|
|
if (XX_MallocSmartInit() != E_OK)
|
|
return (ENXIO);
|
|
|
|
XX_TrackInit();
|
|
|
|
/* Init locks */
|
|
mtx_init(&sc->sc_lock, device_get_nameunit(dev),
|
|
"DTSEC Global Lock", MTX_DEF);
|
|
|
|
mtx_init(&sc->sc_mii_lock, device_get_nameunit(dev),
|
|
"DTSEC MII Lock", MTX_DEF);
|
|
|
|
/* Init callouts */
|
|
callout_init(&sc->sc_tick_callout, CALLOUT_MPSAFE);
|
|
|
|
/* Read configuraton */
|
|
if ((error = fman_get_handle(&sc->sc_fmh)) != 0)
|
|
return (error);
|
|
|
|
if ((error = fman_get_muram_handle(&sc->sc_muramh)) != 0)
|
|
return (error);
|
|
|
|
if ((error = fman_get_bushandle(&sc->sc_fm_base)) != 0)
|
|
return (error);
|
|
|
|
/* Configure working mode */
|
|
dtsec_configure_mode(sc);
|
|
|
|
/* If we are working in regular mode configure BMAN and QMAN */
|
|
if (sc->sc_mode == DTSEC_MODE_REGULAR) {
|
|
/* Create RX buffer pool */
|
|
error = dtsec_rm_pool_rx_init(sc);
|
|
if (error != 0)
|
|
return (EIO);
|
|
|
|
/* Create RX frame queue range */
|
|
error = dtsec_rm_fqr_rx_init(sc);
|
|
if (error != 0)
|
|
return (EIO);
|
|
|
|
/* Create frame info pool */
|
|
error = dtsec_rm_fi_pool_init(sc);
|
|
if (error != 0)
|
|
return (EIO);
|
|
|
|
/* Create TX frame queue range */
|
|
error = dtsec_rm_fqr_tx_init(sc);
|
|
if (error != 0)
|
|
return (EIO);
|
|
}
|
|
|
|
/* Init FMan MAC module. */
|
|
error = dtsec_fm_mac_init(sc, sc->sc_mac_addr);
|
|
if (error != 0) {
|
|
dtsec_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/*
|
|
* XXX: All phys are connected to MDIO interface of the first dTSEC
|
|
* device (dTSEC0). We have to save handle to the FM_MAC instance of
|
|
* dTSEC0, which is used later during phy's registers accesses. Another
|
|
* option would be adding new property to DTS pointing to correct dTSEC
|
|
* instance, of which FM_MAC handle has to be used for phy's registers
|
|
* accesses. We did not want to add new properties to DTS, thus this
|
|
* quite ugly hack.
|
|
*/
|
|
if (sc->sc_eth_id == 0)
|
|
dtsec_mdio_mac_handle = sc->sc_mach;
|
|
if (sc->sc_hidden)
|
|
return (0);
|
|
|
|
/* Init FMan TX port */
|
|
error = sc->sc_port_tx_init(sc, device_get_unit(sc->sc_dev));
|
|
if (error != 0) {
|
|
dtsec_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Init FMan RX port */
|
|
error = sc->sc_port_rx_init(sc, device_get_unit(sc->sc_dev));
|
|
if (error != 0) {
|
|
dtsec_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Create network interface for upper layers */
|
|
ifp = sc->sc_ifnet = if_alloc(IFT_ETHER);
|
|
if (ifp == NULL) {
|
|
device_printf(sc->sc_dev, "if_alloc() failed.\n");
|
|
dtsec_detach(dev);
|
|
return (ENOMEM);
|
|
}
|
|
|
|
ifp->if_softc = sc;
|
|
ifp->if_mtu = ETHERMTU; /* TODO: Configure */
|
|
ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST;
|
|
ifp->if_init = dtsec_if_init;
|
|
ifp->if_start = dtsec_if_start;
|
|
ifp->if_ioctl = dtsec_if_ioctl;
|
|
ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
|
|
|
|
if (sc->sc_phy_addr >= 0)
|
|
if_initname(ifp, device_get_name(sc->sc_dev),
|
|
device_get_unit(sc->sc_dev));
|
|
else
|
|
if_initname(ifp, "dtsec_phy", device_get_unit(sc->sc_dev));
|
|
|
|
/* TODO */
|
|
#if 0
|
|
IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1);
|
|
ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1;
|
|
IFQ_SET_READY(&ifp->if_snd);
|
|
#endif
|
|
ifp->if_capabilities = 0; /* TODO: Check */
|
|
ifp->if_capenable = ifp->if_capabilities;
|
|
|
|
/* Attach PHY(s) */
|
|
error = mii_attach(sc->sc_dev, &sc->sc_mii_dev, ifp, dtsec_ifmedia_upd,
|
|
dtsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->sc_phy_addr,
|
|
MII_OFFSET_ANY, 0);
|
|
if (error) {
|
|
device_printf(sc->sc_dev, "attaching PHYs failed: %d\n", error);
|
|
dtsec_detach(sc->sc_dev);
|
|
return (error);
|
|
}
|
|
sc->sc_mii = device_get_softc(sc->sc_mii_dev);
|
|
|
|
/* Attach to stack */
|
|
ether_ifattach(ifp, sc->sc_mac_addr);
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
dtsec_detach(device_t dev)
|
|
{
|
|
struct dtsec_softc *sc;
|
|
if_t ifp;
|
|
|
|
sc = device_get_softc(dev);
|
|
ifp = sc->sc_ifnet;
|
|
|
|
if (device_is_attached(dev)) {
|
|
ether_ifdetach(ifp);
|
|
/* Shutdown interface */
|
|
DTSEC_LOCK(sc);
|
|
dtsec_if_deinit_locked(sc);
|
|
DTSEC_UNLOCK(sc);
|
|
}
|
|
|
|
if (sc->sc_ifnet) {
|
|
if_free(sc->sc_ifnet);
|
|
sc->sc_ifnet = NULL;
|
|
}
|
|
|
|
if (sc->sc_mode == DTSEC_MODE_REGULAR) {
|
|
/* Free RX/TX FQRs */
|
|
dtsec_rm_fqr_rx_free(sc);
|
|
dtsec_rm_fqr_tx_free(sc);
|
|
|
|
/* Free frame info pool */
|
|
dtsec_rm_fi_pool_free(sc);
|
|
|
|
/* Free RX buffer pool */
|
|
dtsec_rm_pool_rx_free(sc);
|
|
}
|
|
|
|
dtsec_fm_mac_free(sc);
|
|
dtsec_fm_port_free_both(sc);
|
|
|
|
/* Destroy lock */
|
|
mtx_destroy(&sc->sc_lock);
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
dtsec_suspend(device_t dev)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
dtsec_resume(device_t dev)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
dtsec_shutdown(device_t dev)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
/** @} */
|
|
|
|
|
|
/**
|
|
* @group MII bus interface.
|
|
* @{
|
|
*/
|
|
int
|
|
dtsec_miibus_readreg(device_t dev, int phy, int reg)
|
|
{
|
|
struct dtsec_softc *sc;
|
|
uint16_t data;
|
|
t_Error error;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (phy != sc->sc_phy_addr)
|
|
return (0xFFFF);
|
|
|
|
DTSEC_MII_LOCK(sc);
|
|
error = FM_MAC_MII_ReadPhyReg(dtsec_mdio_mac_handle, phy, reg, &data);
|
|
DTSEC_MII_UNLOCK(sc);
|
|
if (error != E_OK) {
|
|
device_printf(dev, "Error while reading from PHY (NetCommSw "
|
|
"error: %d)\n", error);
|
|
return (0xFFFF);
|
|
}
|
|
|
|
return ((int)data);
|
|
}
|
|
|
|
int
|
|
dtsec_miibus_writereg(device_t dev, int phy, int reg, int value)
|
|
{
|
|
struct dtsec_softc *sc;
|
|
t_Error error;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (phy != sc->sc_phy_addr)
|
|
return (EINVAL);
|
|
|
|
DTSEC_MII_LOCK(sc);
|
|
error = FM_MAC_MII_WritePhyReg(dtsec_mdio_mac_handle, phy, reg, value);
|
|
DTSEC_MII_UNLOCK(sc);
|
|
if (error != E_OK) {
|
|
device_printf(dev, "Error while writing to PHY (NetCommSw "
|
|
"error: %d).\n", error);
|
|
return (EIO);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
dtsec_miibus_statchg(device_t dev)
|
|
{
|
|
struct dtsec_softc *sc;
|
|
e_EnetSpeed speed;
|
|
bool duplex;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
DTSEC_LOCK_ASSERT(sc);
|
|
|
|
duplex = ((sc->sc_mii->mii_media_active & IFM_GMASK) == IFM_FDX);
|
|
|
|
switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) {
|
|
case IFM_1000_T:
|
|
case IFM_1000_SX:
|
|
speed = e_ENET_SPEED_1000;
|
|
break;
|
|
|
|
case IFM_100_TX:
|
|
speed = e_ENET_SPEED_100;
|
|
break;
|
|
|
|
case IFM_10_T:
|
|
speed = e_ENET_SPEED_10;
|
|
break;
|
|
|
|
default:
|
|
speed = e_ENET_SPEED_10;
|
|
}
|
|
|
|
error = FM_MAC_AdjustLink(sc->sc_mach, speed, duplex);
|
|
if (error != E_OK)
|
|
device_printf(sc->sc_dev, "error while adjusting MAC speed.\n");
|
|
}
|
|
/** @} */
|