* the mips74k cores only need EHB (which is 'sll $0, $0, 3')
here; NOPs don't actually work.
* add EHB as the last NOP for the default barriers/hazards;
that is "better" behaviour and should work on a wider
variety of processors.
This allows the existing (icky) TLB code to work, allowing
the AR9344 SoC (mips74k) to actually get through kernel startup.
Tested:
* AR9344 SoC - (mips74k)
* AR9331 SoC - (mips24k)
TODO:
* test on mips4k CPUs, just to be sure.
* document that sll $0, $0, 3 is actually "EHB" and that it
falls back to being a NOP for pre-mips32r1.
* mips24k has an errata that we currently don't correctly explicitly
state - ie, that after DERET/ERET, the only valid instruction is
a NOP.
Reviewed by: imp@
Approved by: re@ (gjb)
4cfbfdd4b3