1537078d8f
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
657 lines
18 KiB
C
657 lines
18 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-2-Clause-NetBSD
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*
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* Copyright (c) 2011 Marius Strobl <marius@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $NetBSD: pcscp.c,v 1.45 2010/11/13 13:52:08 uebayasi Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center; Izumi Tsutsui.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* esp_pci.c: device dependent code for AMD Am53c974 (PCscsi-PCI)
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* written by Izumi Tsutsui <tsutsui@NetBSD.org>
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*
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* Technical manual available at
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* http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/19113.pdf
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/esp/ncr53c9xreg.h>
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#include <dev/esp/ncr53c9xvar.h>
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#include <dev/esp/am53c974reg.h>
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#define PCI_DEVICE_ID_AMD53C974 0x20201022
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struct esp_pci_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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device_t sc_dev;
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struct resource *sc_res[2];
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#define ESP_PCI_RES_INTR 0
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#define ESP_PCI_RES_IO 1
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bus_dma_tag_t sc_pdmat;
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bus_dma_tag_t sc_xferdmat; /* DMA tag for transfers */
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bus_dmamap_t sc_xferdmam; /* DMA map for transfers */
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void *sc_ih; /* interrupt handler */
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size_t sc_dmasize; /* DMA size */
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void **sc_dmaaddr; /* DMA address */
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size_t *sc_dmalen; /* DMA length */
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int sc_active; /* DMA state */
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int sc_datain; /* DMA Data Direction */
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};
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static struct resource_spec esp_pci_res_spec[] = {
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{ SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* ESP_PCI_RES_INTR */
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{ SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE }, /* ESP_PCI_RES_IO */
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{ -1, 0 }
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};
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#define READ_DMAREG(sc, reg) \
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bus_read_4((sc)->sc_res[ESP_PCI_RES_IO], (reg))
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#define WRITE_DMAREG(sc, reg, var) \
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bus_write_4((sc)->sc_res[ESP_PCI_RES_IO], (reg), (var))
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#define READ_ESPREG(sc, reg) \
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bus_read_1((sc)->sc_res[ESP_PCI_RES_IO], (reg) << 2)
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#define WRITE_ESPREG(sc, reg, val) \
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bus_write_1((sc)->sc_res[ESP_PCI_RES_IO], (reg) << 2, (val))
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static int esp_pci_probe(device_t);
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static int esp_pci_attach(device_t);
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static int esp_pci_detach(device_t);
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static int esp_pci_suspend(device_t);
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static int esp_pci_resume(device_t);
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static device_method_t esp_pci_methods[] = {
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DEVMETHOD(device_probe, esp_pci_probe),
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DEVMETHOD(device_attach, esp_pci_attach),
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DEVMETHOD(device_detach, esp_pci_detach),
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DEVMETHOD(device_suspend, esp_pci_suspend),
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DEVMETHOD(device_resume, esp_pci_resume),
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DEVMETHOD_END
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};
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static driver_t esp_pci_driver = {
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"esp",
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esp_pci_methods,
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sizeof(struct esp_pci_softc)
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};
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DRIVER_MODULE(esp, pci, esp_pci_driver, esp_devclass, 0, 0);
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MODULE_DEPEND(esp, pci, 1, 1, 1);
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/*
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* Functions and the switch for the MI code
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*/
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static void esp_pci_dma_go(struct ncr53c9x_softc *);
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static int esp_pci_dma_intr(struct ncr53c9x_softc *);
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static int esp_pci_dma_isactive(struct ncr53c9x_softc *);
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static int esp_pci_dma_isintr(struct ncr53c9x_softc *);
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static void esp_pci_dma_reset(struct ncr53c9x_softc *);
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static int esp_pci_dma_setup(struct ncr53c9x_softc *, void **, size_t *,
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int, size_t *);
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static void esp_pci_dma_stop(struct ncr53c9x_softc *);
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static void esp_pci_write_reg(struct ncr53c9x_softc *, int, uint8_t);
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static uint8_t esp_pci_read_reg(struct ncr53c9x_softc *, int);
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static void esp_pci_xfermap(void *arg, bus_dma_segment_t *segs, int nseg,
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int error);
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static struct ncr53c9x_glue esp_pci_glue = {
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esp_pci_read_reg,
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esp_pci_write_reg,
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esp_pci_dma_isintr,
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esp_pci_dma_reset,
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esp_pci_dma_intr,
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esp_pci_dma_setup,
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esp_pci_dma_go,
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esp_pci_dma_stop,
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esp_pci_dma_isactive,
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};
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static int
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esp_pci_probe(device_t dev)
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{
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if (pci_get_devid(dev) == PCI_DEVICE_ID_AMD53C974) {
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device_set_desc(dev, "AMD Am53C974 Fast-SCSI");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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static int
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esp_pci_attach(device_t dev)
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{
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struct esp_pci_softc *esc;
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struct ncr53c9x_softc *sc;
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int error;
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esc = device_get_softc(dev);
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sc = &esc->sc_ncr53c9x;
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NCR_LOCK_INIT(sc);
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esc->sc_dev = dev;
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sc->sc_glue = &esp_pci_glue;
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pci_enable_busmaster(dev);
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error = bus_alloc_resources(dev, esp_pci_res_spec, esc->sc_res);
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if (error != 0) {
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device_printf(dev, "failed to allocate resources\n");
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bus_release_resources(dev, esp_pci_res_spec, esc->sc_res);
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return (error);
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}
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error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
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BUS_SPACE_MAXSIZE_32BIT, BUS_SPACE_UNRESTRICTED,
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BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &esc->sc_pdmat);
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if (error != 0) {
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device_printf(dev, "cannot create parent DMA tag\n");
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goto fail_res;
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}
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* Set up static configuration info.
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*
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* XXX we should read the configuration from the EEPROM.
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*/
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sc->sc_id = 7;
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
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sc->sc_cfg3 = NCRAMDCFG3_IDM | NCRAMDCFG3_FCLK;
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sc->sc_cfg4 = NCRAMDCFG4_GE12NS | NCRAMDCFG4_RADE;
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sc->sc_rev = NCR_VARIANT_AM53C974;
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sc->sc_features = NCR_F_FASTSCSI | NCR_F_DMASELECT;
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sc->sc_cfg3_fscsi = NCRAMDCFG3_FSCSI;
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sc->sc_freq = 40; /* MHz */
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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sc->sc_maxxfer = DFLTPHYS; /* see below */
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sc->sc_maxoffset = 15;
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sc->sc_extended_geom = 1;
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#define MDL_SEG_SIZE 0x1000 /* 4kbyte per segment */
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/*
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* Create the DMA tag and map for the data transfers.
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*
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* Note: given that bus_dma(9) only adheres to the requested alignment
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* for the first segment (and that also only for bus_dmamem_alloc()ed
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* DMA maps) we can't use the Memory Descriptor List. However, also
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* when not using the MDL, the maximum transfer size apparently is
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* limited to 4k so we have to split transfers up, which plain sucks.
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*/
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error = bus_dma_tag_create(esc->sc_pdmat, PAGE_SIZE, 0,
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BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
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MDL_SEG_SIZE, 1, MDL_SEG_SIZE, BUS_DMA_ALLOCNOW,
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busdma_lock_mutex, &sc->sc_lock, &esc->sc_xferdmat);
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if (error != 0) {
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device_printf(dev, "cannot create transfer DMA tag\n");
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goto fail_pdmat;
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}
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error = bus_dmamap_create(esc->sc_xferdmat, 0, &esc->sc_xferdmam);
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if (error != 0) {
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device_printf(dev, "cannot create transfer DMA map\n");
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goto fail_xferdmat;
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}
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error = bus_setup_intr(dev, esc->sc_res[ESP_PCI_RES_INTR],
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INTR_MPSAFE | INTR_TYPE_CAM, NULL, ncr53c9x_intr, sc,
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&esc->sc_ih);
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if (error != 0) {
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device_printf(dev, "cannot set up interrupt\n");
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goto fail_xferdmam;
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}
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/* Do the common parts of attachment. */
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sc->sc_dev = esc->sc_dev;
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error = ncr53c9x_attach(sc);
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if (error != 0) {
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device_printf(esc->sc_dev, "ncr53c9x_attach failed\n");
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goto fail_intr;
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}
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return (0);
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fail_intr:
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bus_teardown_intr(esc->sc_dev, esc->sc_res[ESP_PCI_RES_INTR],
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esc->sc_ih);
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fail_xferdmam:
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bus_dmamap_destroy(esc->sc_xferdmat, esc->sc_xferdmam);
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fail_xferdmat:
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bus_dma_tag_destroy(esc->sc_xferdmat);
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fail_pdmat:
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bus_dma_tag_destroy(esc->sc_pdmat);
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fail_res:
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bus_release_resources(dev, esp_pci_res_spec, esc->sc_res);
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NCR_LOCK_DESTROY(sc);
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return (error);
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}
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static int
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esp_pci_detach(device_t dev)
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{
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struct ncr53c9x_softc *sc;
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struct esp_pci_softc *esc;
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int error;
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esc = device_get_softc(dev);
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sc = &esc->sc_ncr53c9x;
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bus_teardown_intr(esc->sc_dev, esc->sc_res[ESP_PCI_RES_INTR],
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esc->sc_ih);
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error = ncr53c9x_detach(sc);
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if (error != 0)
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return (error);
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bus_dmamap_destroy(esc->sc_xferdmat, esc->sc_xferdmam);
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bus_dma_tag_destroy(esc->sc_xferdmat);
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bus_dma_tag_destroy(esc->sc_pdmat);
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bus_release_resources(dev, esp_pci_res_spec, esc->sc_res);
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NCR_LOCK_DESTROY(sc);
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return (0);
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}
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static int
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esp_pci_suspend(device_t dev)
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{
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return (ENXIO);
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}
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static int
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esp_pci_resume(device_t dev)
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{
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return (ENXIO);
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}
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static void
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esp_pci_xfermap(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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{
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struct esp_pci_softc *esc = (struct esp_pci_softc *)arg;
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if (error != 0)
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return;
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KASSERT(nsegs == 1, ("%s: bad transfer segment count %d", __func__,
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nsegs));
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KASSERT(segs[0].ds_len <= MDL_SEG_SIZE,
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("%s: bad transfer segment length %ld", __func__,
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(long)segs[0].ds_len));
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/* Program the DMA Starting Physical Address. */
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WRITE_DMAREG(esc, DMA_SPA, segs[0].ds_addr);
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}
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/*
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* Glue functions
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*/
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static uint8_t
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esp_pci_read_reg(struct ncr53c9x_softc *sc, int reg)
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{
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struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
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return (READ_ESPREG(esc, reg));
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}
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static void
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esp_pci_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t v)
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{
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struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
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WRITE_ESPREG(esc, reg, v);
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}
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static int
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esp_pci_dma_isintr(struct ncr53c9x_softc *sc)
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{
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struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
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return (READ_ESPREG(esc, NCR_STAT) & NCRSTAT_INT) != 0;
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}
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static void
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esp_pci_dma_reset(struct ncr53c9x_softc *sc)
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{
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struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
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WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE);
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esc->sc_active = 0;
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}
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static int
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esp_pci_dma_intr(struct ncr53c9x_softc *sc)
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{
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struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
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bus_dma_tag_t xferdmat;
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bus_dmamap_t xferdmam;
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size_t dmasize;
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int datain, i, resid, trans;
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uint32_t dmastat;
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char *p = NULL;
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xferdmat = esc->sc_xferdmat;
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xferdmam = esc->sc_xferdmam;
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datain = esc->sc_datain;
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dmastat = READ_DMAREG(esc, DMA_STAT);
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if ((dmastat & DMASTAT_ERR) != 0) {
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/* XXX not tested... */
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WRITE_DMAREG(esc, DMA_CMD, DMACMD_ABORT | (datain != 0 ?
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DMACMD_DIR : 0));
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device_printf(esc->sc_dev, "DMA error detected; Aborting.\n");
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bus_dmamap_sync(xferdmat, xferdmam, datain != 0 ?
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BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(xferdmat, xferdmam);
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return (-1);
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}
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if ((dmastat & DMASTAT_ABT) != 0) {
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/* XXX what should be done? */
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device_printf(esc->sc_dev, "DMA aborted.\n");
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WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain != 0 ?
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DMACMD_DIR : 0));
|
|
esc->sc_active = 0;
|
|
return (0);
|
|
}
|
|
|
|
KASSERT(esc->sc_active != 0, ("%s: DMA wasn't active", __func__));
|
|
|
|
/* DMA has stopped. */
|
|
|
|
esc->sc_active = 0;
|
|
|
|
dmasize = esc->sc_dmasize;
|
|
if (dmasize == 0) {
|
|
/* A "Transfer Pad" operation completed. */
|
|
NCR_DMA(("%s: discarded %d bytes (tcl=%d, tcm=%d)\n",
|
|
__func__, READ_ESPREG(esc, NCR_TCL) |
|
|
(READ_ESPREG(esc, NCR_TCM) << 8),
|
|
READ_ESPREG(esc, NCR_TCL), READ_ESPREG(esc, NCR_TCM)));
|
|
return (0);
|
|
}
|
|
|
|
resid = 0;
|
|
/*
|
|
* If a transfer onto the SCSI bus gets interrupted by the device
|
|
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
|
|
* as residual since the ESP counter registers get decremented as
|
|
* bytes are clocked into the FIFO.
|
|
*/
|
|
if (datain == 0 &&
|
|
(resid = (READ_ESPREG(esc, NCR_FFLAG) & NCRFIFO_FF)) != 0)
|
|
NCR_DMA(("%s: empty esp FIFO of %d ", __func__, resid));
|
|
|
|
if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
|
|
/*
|
|
* "Terminal count" is off, so read the residue
|
|
* out of the ESP counter registers.
|
|
*/
|
|
if (datain != 0) {
|
|
resid = READ_ESPREG(esc, NCR_FFLAG) & NCRFIFO_FF;
|
|
while (resid > 1)
|
|
resid =
|
|
READ_ESPREG(esc, NCR_FFLAG) & NCRFIFO_FF;
|
|
WRITE_DMAREG(esc, DMA_CMD, DMACMD_BLAST | DMACMD_DIR);
|
|
|
|
for (i = 0; i < 0x8000; i++) /* XXX 0x8000 ? */
|
|
if ((READ_DMAREG(esc, DMA_STAT) &
|
|
DMASTAT_BCMP) != 0)
|
|
break;
|
|
|
|
/* See the below comments... */
|
|
if (resid != 0)
|
|
p = *esc->sc_dmaaddr;
|
|
}
|
|
|
|
resid += READ_ESPREG(esc, NCR_TCL) |
|
|
(READ_ESPREG(esc, NCR_TCM) << 8) |
|
|
(READ_ESPREG(esc, NCR_TCH) << 16);
|
|
} else
|
|
while ((dmastat & DMASTAT_DONE) == 0)
|
|
dmastat = READ_DMAREG(esc, DMA_STAT);
|
|
|
|
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain != 0 ?
|
|
DMACMD_DIR : 0));
|
|
|
|
/* Sync the transfer buffer. */
|
|
bus_dmamap_sync(xferdmat, xferdmam, datain != 0 ?
|
|
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(xferdmat, xferdmam);
|
|
|
|
trans = dmasize - resid;
|
|
|
|
/*
|
|
* From the technical manual notes:
|
|
*
|
|
* "In some odd byte conditions, one residual byte will be left
|
|
* in the SCSI FIFO, and the FIFO flags will never count to 0.
|
|
* When this happens, the residual byte should be retrieved
|
|
* via PIO following completion of the BLAST operation."
|
|
*/
|
|
if (p != NULL) {
|
|
p += trans;
|
|
*p = READ_ESPREG(esc, NCR_FIFO);
|
|
trans++;
|
|
}
|
|
|
|
if (trans < 0) { /* transferred < 0 ? */
|
|
#if 0
|
|
/*
|
|
* This situation can happen in perfectly normal operation
|
|
* if the ESP is reselected while using DMA to select
|
|
* another target. As such, don't print the warning.
|
|
*/
|
|
device_printf(dev, "xfer (%d) > req (%d)\n", trans, dmasize);
|
|
#endif
|
|
trans = dmasize;
|
|
}
|
|
|
|
NCR_DMA(("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", __func__,
|
|
READ_ESPREG(esc, NCR_TCL), READ_ESPREG(esc, NCR_TCM),
|
|
READ_ESPREG(esc, NCR_TCH), trans, resid));
|
|
|
|
*esc->sc_dmalen -= trans;
|
|
*esc->sc_dmaaddr = (char *)*esc->sc_dmaaddr + trans;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
esp_pci_dma_setup(struct ncr53c9x_softc *sc, void **addr, size_t *len,
|
|
int datain, size_t *dmasize)
|
|
{
|
|
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
|
|
int error;
|
|
|
|
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | (datain != 0 ? DMACMD_DIR :
|
|
0));
|
|
|
|
*dmasize = esc->sc_dmasize = ulmin(*dmasize, MDL_SEG_SIZE);
|
|
esc->sc_dmaaddr = addr;
|
|
esc->sc_dmalen = len;
|
|
esc->sc_datain = datain;
|
|
|
|
/*
|
|
* There's no need to set up DMA for a "Transfer Pad" operation.
|
|
*/
|
|
if (*dmasize == 0)
|
|
return (0);
|
|
|
|
/* Set the transfer length. */
|
|
WRITE_DMAREG(esc, DMA_STC, *dmasize);
|
|
|
|
/*
|
|
* Load the transfer buffer and program the DMA address.
|
|
* Note that the NCR53C9x core can't handle EINPROGRESS so we set
|
|
* BUS_DMA_NOWAIT.
|
|
*/
|
|
error = bus_dmamap_load(esc->sc_xferdmat, esc->sc_xferdmam,
|
|
*esc->sc_dmaaddr, *dmasize, esp_pci_xfermap, sc, BUS_DMA_NOWAIT);
|
|
|
|
return (error);
|
|
}
|
|
|
|
static void
|
|
esp_pci_dma_go(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
|
|
int datain;
|
|
|
|
datain = esc->sc_datain;
|
|
|
|
/* No DMA transfer for a "Transfer Pad" operation */
|
|
if (esc->sc_dmasize == 0)
|
|
return;
|
|
|
|
/* Sync the transfer buffer. */
|
|
bus_dmamap_sync(esc->sc_xferdmat, esc->sc_xferdmam, datain != 0 ?
|
|
BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
|
|
|
|
/* Set the DMA engine to the IDLE state. */
|
|
/* XXX DMA Transfer Interrupt Enable bit is broken? */
|
|
WRITE_DMAREG(esc, DMA_CMD, DMACMD_IDLE | /* DMACMD_INTE | */
|
|
(datain != 0 ? DMACMD_DIR : 0));
|
|
|
|
/* Issue a DMA start command. */
|
|
WRITE_DMAREG(esc, DMA_CMD, DMACMD_START | /* DMACMD_INTE | */
|
|
(datain != 0 ? DMACMD_DIR : 0));
|
|
|
|
esc->sc_active = 1;
|
|
}
|
|
|
|
static void
|
|
esp_pci_dma_stop(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
|
|
|
|
/* DMA stop */
|
|
/* XXX what should we do here ? */
|
|
WRITE_DMAREG(esc, DMA_CMD,
|
|
DMACMD_ABORT | (esc->sc_datain != 0 ? DMACMD_DIR : 0));
|
|
bus_dmamap_unload(esc->sc_xferdmat, esc->sc_xferdmam);
|
|
|
|
esc->sc_active = 0;
|
|
}
|
|
|
|
static int
|
|
esp_pci_dma_isactive(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct esp_pci_softc *esc = (struct esp_pci_softc *)sc;
|
|
|
|
/* XXX should we check esc->sc_active? */
|
|
if ((READ_DMAREG(esc, DMA_CMD) & DMACMD_CMD) != DMACMD_IDLE)
|
|
return (1);
|
|
|
|
return (0);
|
|
}
|