Andrew Turner 405ada37fb Add support for the uart classes to set their default register shift value. ... This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week		2015-04-11 17:16:23 +00:00
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files.rt305x	Turns out the nvram env was common, so move it back up to get PB92 working.	2012-10-23 19:17:43 +00:00
obio.c	Devices that rely on hints or identify routines for discovery need to	2013-10-29 14:07:31 +00:00
obiovar.h
rt305x_dotg.c	Add 64-bit DMA support in the XHCI controller driver.	2015-01-05 20:22:18 +00:00
rt305x_gpio.c	Implement GPIO_GET_BUS() method for all GPIO drivers.	2015-01-31 19:32:14 +00:00
rt305x_gpio.h
rt305x_gpiovar.h	Implement GPIO_GET_BUS() method for all GPIO drivers.	2015-01-31 19:32:14 +00:00
rt305x_ic.c
rt305x_icvar.h
rt305x_machdep.c	Convert remaining {g,s}etenv->kern_{g,s}etenv	2014-10-17 17:34:05 +00:00
rt305x_sysctl.c
rt305x_sysctlvar.h
rt305xreg.h
rt_swreg.h
std.rt305x	o) Use ABI, not ISA_* options, to determine whether to compile bits if libkern	2012-03-12 21:25:32 +00:00
uart_bus_rt305x.c
uart_cpu_rt305x.c
uart_dev_rt305x.c	Add support for the uart classes to set their default register shift value.	2015-04-11 17:16:23 +00:00
uart_dev_rt305x.h