405ada37fb
This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
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adm5120 | ||
alchemy | ||
atheros | ||
beri | ||
cavium | ||
conf | ||
gxemul | ||
idt | ||
include | ||
malta | ||
mips | ||
nlm | ||
rmi | ||
rt305x | ||
sentry5 | ||
sibyte |