br e5126bd290 Support RISC-V implementations that do not manage the A and D bits ... (e.g. RocketChip, lowRISC and derivatives). RISC-V page table entries support A (accessed) and D (dirty) bits. The spec makes hardware support for these bits optional. Implementations that do not manage these bits in hardware raise page faults for accesses to a valid page without A set and writes to a writable page without D set. Check for these types of faults when handling a page fault and fixup the PTE without calling vm_fault if they occur. Reviewed by: jhb, markj Approved by: re (gjb) Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D17424		2018-10-18 15:25:07 +00:00
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conf	Add support for the UART device found in lowRISC system-on-a-chip.	2018-10-12 15:19:41 +00:00
include	Support RISC-V implementations that do not manage the A and D bits	2018-10-18 15:25:07 +00:00
riscv	Support RISC-V implementations that do not manage the A and D bits	2018-10-18 15:25:07 +00:00