6a6acca2aa
up and running. * The MAC FIFO configurations needed updating; * Reset the MDIO block at the same time the MAC block is reset; * The default divisor needs changing as the DB120 runs at a higher base MDIO bus clock compared to other chips. The long-term fix is to allow the system to have a target MDIO bus clock rate and then calculate the most suitable divider to meet that. This will likely need implementing before stable external PHY or switch support can be committed. Tested: * AR9344 (mips74k) * AR9331 (mips24k) |
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adm5120 | ||
alchemy | ||
atheros | ||
beri | ||
cavium | ||
conf | ||
gxemul | ||
idt | ||
include | ||
malta | ||
mips | ||
nlm | ||
rmi | ||
rt305x | ||
sentry5 | ||
sibyte |