kib 3cd0168095 Align IA32_ARCH_CAP MSR definitions and use with SDM rev. 068. ... SDM rev. 068 was released yesterday and it contains the description of the MSR 0x10a IA32_ARCH_CAP. This change adds symbolic definitions for all bits present in the document, and decode them in the CPU identification lines printed on boot. But also, the document defines SSB_NO as bit 4, while FreeBSD used but 2 to detect the need to work-around Speculative Store Bypass issue. Change code to use the bit from SDM. Similarly, the document describes bit 3 as an indicator that L1TF issue is not present, in particular, no L1D flush is needed on VMENTRY. We used RDCL_NO to avoid flushing, and again I changed the code to follow new spec from SDM. In fact my Apollo Lake machine with latest ucode shows this: IA32_ARCH_CAPS=0x19<RDCL_NO,SKIP_L1DFL_VME,SSB_NO> Reviewed by: bwidawsk Sponsored by: The FreeBSD Foundation MFC after: 3 days Differential revision: https://reviews.freebsd.org/D18006		2018-11-16 21:27:11 +00:00
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amd	Merge cases with upper block.	2018-10-31 01:27:44 +00:00
intel	Align IA32_ARCH_CAP MSR definitions and use with SDM rev. 068.	2018-11-16 21:27:11 +00:00
io
vmm_dev.c	- Add the ability to run bhyve(8) within a jail(8).	2018-08-01 00:39:21 +00:00
vmm_host.c
vmm_host.h
vmm_instruction_emul.c	bhyve: emulate CLFLUSH and CLFLUSHOPT.	2018-10-12 15:30:15 +00:00
vmm_ioport.c
vmm_ioport.h
vmm_ktr.h
vmm_lapic.c
vmm_lapic.h
vmm_mem.c
vmm_mem.h
vmm_stat.c
vmm_stat.h
vmm_util.c
vmm_util.h
vmm.c	Handle a guest executing a vm instruction by trapping and raising an	2018-09-27 11:16:19 +00:00
x86.c
x86.h