kib 3cd0168095 Align IA32_ARCH_CAP MSR definitions and use with SDM rev. 068. ... SDM rev. 068 was released yesterday and it contains the description of the MSR 0x10a IA32_ARCH_CAP. This change adds symbolic definitions for all bits present in the document, and decode them in the CPU identification lines printed on boot. But also, the document defines SSB_NO as bit 4, while FreeBSD used but 2 to detect the need to work-around Speculative Store Bypass issue. Change code to use the bit from SDM. Similarly, the document describes bit 3 as an indicator that L1TF issue is not present, in particular, no L1D flush is needed on VMENTRY. We used RDCL_NO to avoid flushing, and again I changed the code to follow new spec from SDM. In fact my Apollo Lake machine with latest ucode shows this: IA32_ARCH_CAPS=0x19<RDCL_NO,SKIP_L1DFL_VME,SSB_NO> Reviewed by: bwidawsk Sponsored by: The FreeBSD Foundation MFC after: 3 days Differential revision: https://reviews.freebsd.org/D18006		2018-11-16 21:27:11 +00:00
..
ept.c
ept.h
vmcs.c
vmcs.h	Provide basic descriptions for VMX exit reason (from "Intel 64 and IA-32	2018-10-27 21:24:28 +00:00
vmx_controls.h
vmx_cpufunc.h
vmx_genassym.c
vmx_msr.c
vmx_msr.h
vmx_support.S	Update L1TF workaround to sustain L1D pollution from NMI.	2018-08-19 18:47:16 +00:00
vmx.c	Align IA32_ARCH_CAP MSR definitions and use with SDM rev. 068.	2018-11-16 21:27:11 +00:00
vmx.h
vtd.c