This part seems to work bug-free with single byte TX/RX buffer alignment. This drops the CPU requirement to bridge 100mbit iperf from 100% CPU to ~ 50% CPU. Tested: * AP121 (AR9330) SoC, highly magic netbooted kernel + USB rootfs due to 4mb flash, 16mb RAM; doing bridging between arge0 and arge1. Notes: * Yes, I likely can also turn this on for the AR934x SoC family now. But since hardware design apparently follows similar branching strategies to software design, I'll go and make sure all the AR934x's that made it out into shipping products work before I flip it on.
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