492b489d72
H/W not de-asserting the interrupt at all. On x86, and because of the
following conditions, this results in a hard hang with interrupts disabled:
1. The uart(4) driver uses a spin lock to protect against concurrent
access to the H/W. Spin locks disable and restore interrupts.
2. Restoring the interrupt on x86 always writes the flags register. Even
if we're restoring the interrupt from disabled to disabled.
3. The x86 CPU has a short window in which interrupts are enabled when the
flags register is written.
4. The uart(4) driver registers a fast interrupt by default.
To catch this case, we first try to clear any pending H/W interrupts and in
particular, before setting up the interrupt. This makes sure the interrupt
is masked on the PIC. The interrupt handler now has a limit set on the
number of iterations it'll go through to clear interrupt conditions. If the
limit is hit, the handler will return FILTER_SCHEDULE_THREAD. The attach
function will check for this return code and avoid setting up the interrupt
and foce polling in that case.
Obtained from: Juniper Networks, Inc.
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|---|---|---|
| .. | ||
| uart_bus_acpi.c | ||
| uart_bus_ebus.c | ||
| uart_bus_fdt.c | ||
| uart_bus_isa.c | ||
| uart_bus_pccard.c | ||
| uart_bus_pci.c | ||
| uart_bus_puc.c | ||
| uart_bus_scc.c | ||
| uart_bus.h | ||
| uart_core.c | ||
| uart_cpu_fdt.c | ||
| uart_cpu_ia64.c | ||
| uart_cpu_pc98.c | ||
| uart_cpu_powerpc.c | ||
| uart_cpu_sparc64.c | ||
| uart_cpu_x86.c | ||
| uart_cpu.h | ||
| uart_dbg.c | ||
| uart_dev_imx5xx.h | ||
| uart_dev_imx.c | ||
| uart_dev_lpc.c | ||
| uart_dev_ns8250.c | ||
| uart_dev_pl011.c | ||
| uart_dev_quicc.c | ||
| uart_dev_sab82532.c | ||
| uart_dev_z8530.c | ||
| uart_if.m | ||
| uart_kbd_sun_tables.h | ||
| uart_kbd_sun.c | ||
| uart_kbd_sun.h | ||
| uart_subr.c | ||
| uart_tty.c | ||
| uart.h | ||