626 lines
23 KiB
C
626 lines
23 KiB
C
/*-
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* Copyright (c) 2011 Chelsio Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __CHELSIO_COMMON_H
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#define __CHELSIO_COMMON_H
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#include "t4_hw.h"
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enum {
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MAX_NPORTS = 4, /* max # of ports */
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SERNUM_LEN = 24, /* Serial # length */
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EC_LEN = 16, /* E/C length */
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ID_LEN = 16, /* ID length */
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PN_LEN = 16, /* Part Number length */
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MACADDR_LEN = 12, /* MAC Address length */
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};
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enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
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enum {
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MEMWIN0_APERTURE = 2048,
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MEMWIN0_BASE = 0x1b800,
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MEMWIN1_APERTURE = 32768,
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MEMWIN1_BASE = 0x28000,
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MEMWIN2_APERTURE_T4 = 65536,
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MEMWIN2_BASE_T4 = 0x30000,
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MEMWIN2_APERTURE_T5 = 128 * 1024,
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MEMWIN2_BASE_T5 = 0x60000,
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};
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enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
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enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
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enum {
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PAUSE_RX = 1 << 0,
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PAUSE_TX = 1 << 1,
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PAUSE_AUTONEG = 1 << 2
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};
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struct memwin {
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uint32_t base;
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uint32_t aperture;
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};
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struct port_stats {
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u64 tx_octets; /* total # of octets in good frames */
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u64 tx_frames; /* all good frames */
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u64 tx_bcast_frames; /* all broadcast frames */
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u64 tx_mcast_frames; /* all multicast frames */
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u64 tx_ucast_frames; /* all unicast frames */
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u64 tx_error_frames; /* all error frames */
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u64 tx_frames_64; /* # of Tx frames in a particular range */
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u64 tx_frames_65_127;
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u64 tx_frames_128_255;
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u64 tx_frames_256_511;
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u64 tx_frames_512_1023;
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u64 tx_frames_1024_1518;
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u64 tx_frames_1519_max;
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u64 tx_drop; /* # of dropped Tx frames */
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u64 tx_pause; /* # of transmitted pause frames */
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u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
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u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
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u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
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u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
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u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
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u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
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u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
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u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
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u64 rx_octets; /* total # of octets in good frames */
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u64 rx_frames; /* all good frames */
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u64 rx_bcast_frames; /* all broadcast frames */
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u64 rx_mcast_frames; /* all multicast frames */
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u64 rx_ucast_frames; /* all unicast frames */
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u64 rx_too_long; /* # of frames exceeding MTU */
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u64 rx_jabber; /* # of jabber frames */
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u64 rx_fcs_err; /* # of received frames with bad FCS */
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u64 rx_len_err; /* # of received frames with length error */
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u64 rx_symbol_err; /* symbol errors */
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u64 rx_runt; /* # of short frames */
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u64 rx_frames_64; /* # of Rx frames in a particular range */
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u64 rx_frames_65_127;
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u64 rx_frames_128_255;
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u64 rx_frames_256_511;
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u64 rx_frames_512_1023;
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u64 rx_frames_1024_1518;
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u64 rx_frames_1519_max;
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u64 rx_pause; /* # of received pause frames */
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u64 rx_ppp0; /* # of received PPP prio 0 frames */
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u64 rx_ppp1; /* # of received PPP prio 1 frames */
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u64 rx_ppp2; /* # of received PPP prio 2 frames */
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u64 rx_ppp3; /* # of received PPP prio 3 frames */
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u64 rx_ppp4; /* # of received PPP prio 4 frames */
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u64 rx_ppp5; /* # of received PPP prio 5 frames */
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u64 rx_ppp6; /* # of received PPP prio 6 frames */
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u64 rx_ppp7; /* # of received PPP prio 7 frames */
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u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
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u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
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u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
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u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
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u64 rx_trunc0; /* buffer-group 0 truncated packets */
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u64 rx_trunc1; /* buffer-group 1 truncated packets */
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u64 rx_trunc2; /* buffer-group 2 truncated packets */
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u64 rx_trunc3; /* buffer-group 3 truncated packets */
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};
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struct lb_port_stats {
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u64 octets;
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u64 frames;
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u64 bcast_frames;
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u64 mcast_frames;
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u64 ucast_frames;
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u64 error_frames;
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u64 frames_64;
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u64 frames_65_127;
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u64 frames_128_255;
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u64 frames_256_511;
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u64 frames_512_1023;
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u64 frames_1024_1518;
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u64 frames_1519_max;
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u64 drop;
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u64 ovflow0;
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u64 ovflow1;
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u64 ovflow2;
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u64 ovflow3;
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u64 trunc0;
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u64 trunc1;
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u64 trunc2;
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u64 trunc3;
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};
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struct tp_tcp_stats {
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u32 tcpOutRsts;
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u64 tcpInSegs;
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u64 tcpOutSegs;
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u64 tcpRetransSegs;
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};
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struct tp_usm_stats {
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u32 frames;
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u32 drops;
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u64 octets;
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};
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struct tp_fcoe_stats {
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u32 framesDDP;
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u32 framesDrop;
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u64 octetsDDP;
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};
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struct tp_err_stats {
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u32 macInErrs[4];
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u32 hdrInErrs[4];
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u32 tcpInErrs[4];
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u32 tnlCongDrops[4];
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u32 ofldChanDrops[4];
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u32 tnlTxDrops[4];
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u32 ofldVlanDrops[4];
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u32 tcp6InErrs[4];
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u32 ofldNoNeigh;
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u32 ofldCongDefer;
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};
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struct tp_proxy_stats {
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u32 proxy[4];
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};
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struct tp_cpl_stats {
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u32 req[4];
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u32 rsp[4];
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};
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struct tp_rdma_stats {
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u32 rqe_dfr_mod;
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u32 rqe_dfr_pkt;
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};
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struct tp_params {
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unsigned int ntxchan; /* # of Tx channels */
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unsigned int tre; /* log2 of core clocks per TP tick */
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unsigned int dack_re; /* DACK timer resolution */
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unsigned int la_mask; /* what events are recorded by TP LA */
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unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
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uint32_t vlan_pri_map;
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uint32_t ingress_config;
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int8_t vlan_shift;
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int8_t vnic_shift;
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int8_t port_shift;
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int8_t protocol_shift;
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};
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struct vpd_params {
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unsigned int cclk;
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u8 ec[EC_LEN + 1];
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u8 sn[SERNUM_LEN + 1];
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u8 id[ID_LEN + 1];
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u8 pn[PN_LEN + 1];
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u8 na[MACADDR_LEN + 1];
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};
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struct pci_params {
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unsigned int vpd_cap_addr;
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unsigned int mps;
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unsigned short speed;
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unsigned short width;
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};
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/*
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* Firmware device log.
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*/
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struct devlog_params {
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u32 memtype; /* which memory (FW_MEMTYPE_* ) */
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u32 start; /* start of log in firmware memory */
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u32 size; /* size of log */
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};
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struct adapter_params {
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struct tp_params tp;
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struct vpd_params vpd;
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struct pci_params pci;
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struct devlog_params devlog;
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unsigned int sf_size; /* serial flash size in bytes */
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unsigned int sf_nsec; /* # of flash sectors */
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unsigned int fw_vers;
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unsigned int tp_vers;
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unsigned short mtus[NMTUS];
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unsigned short a_wnd[NCCTRL_WIN];
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unsigned short b_wnd[NCCTRL_WIN];
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u_int ftid_min;
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u_int ftid_max;
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u_int etid_min;
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u_int netids;
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unsigned int cim_la_size;
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uint8_t nports; /* # of ethernet ports */
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uint8_t portvec;
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unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */
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unsigned int rev:4; /* chip revision */
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unsigned int fpga:1; /* this is an FPGA */
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unsigned int offload:1; /* hw is TOE capable, fw has divvied up card
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resources for TOE operation. */
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unsigned int bypass:1; /* this is a bypass card */
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unsigned int ethoffload:1;
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unsigned int ofldq_wr_cred;
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unsigned int eo_wr_cred;
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};
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#define CHELSIO_T4 0x4
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#define CHELSIO_T5 0x5
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struct trace_params {
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u32 data[TRACE_LEN / 4];
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u32 mask[TRACE_LEN / 4];
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unsigned short snap_len;
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unsigned short min_len;
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unsigned char skip_ofst;
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unsigned char skip_len;
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unsigned char invert;
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unsigned char port;
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};
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struct link_config {
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unsigned short supported; /* link capabilities */
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unsigned short advertising; /* advertised capabilities */
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unsigned short requested_speed; /* speed user has requested */
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unsigned short speed; /* actual link speed */
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unsigned char requested_fc; /* flow control user has requested */
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unsigned char fc; /* actual link flow control */
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unsigned char autoneg; /* autonegotiating? */
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unsigned char link_ok; /* link up? */
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};
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#include "adapter.h"
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#ifndef PCI_VENDOR_ID_CHELSIO
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# define PCI_VENDOR_ID_CHELSIO 0x1425
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#endif
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#define for_each_port(adapter, iter) \
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for (iter = 0; iter < (adapter)->params.nports; ++iter)
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static inline int is_ftid(const struct adapter *sc, u_int tid)
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{
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return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max);
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}
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static inline int is_etid(const struct adapter *sc, u_int tid)
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{
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return (tid >= sc->params.etid_min);
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}
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static inline int is_offload(const struct adapter *adap)
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{
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return adap->params.offload;
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}
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static inline int is_ethoffload(const struct adapter *adap)
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{
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return adap->params.ethoffload;
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}
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static inline int chip_id(struct adapter *adap)
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{
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return adap->params.chipid;
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}
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static inline int chip_rev(struct adapter *adap)
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{
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return adap->params.rev;
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}
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static inline int is_t4(struct adapter *adap)
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{
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return adap->params.chipid == CHELSIO_T4;
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}
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static inline int is_t5(struct adapter *adap)
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{
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return adap->params.chipid == CHELSIO_T5;
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}
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static inline int is_fpga(struct adapter *adap)
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{
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return adap->params.fpga;
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}
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static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
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{
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return adap->params.vpd.cclk / 1000;
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}
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static inline unsigned int us_to_core_ticks(const struct adapter *adap,
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unsigned int us)
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{
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return (us * adap->params.vpd.cclk) / 1000;
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}
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static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
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unsigned int ticks)
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{
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return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
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}
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void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
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int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, int polarity,
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int attempts, int delay, u32 *valp);
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static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
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int polarity, int attempts, int delay)
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{
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return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
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delay, NULL);
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}
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int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
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void *rpl, bool sleep_ok);
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static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
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int size, void *rpl)
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{
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return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
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}
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static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
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int size, void *rpl)
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{
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return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
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}
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void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
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unsigned int data_reg, u32 *vals, unsigned int nregs,
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unsigned int start_idx);
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void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
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unsigned int data_reg, const u32 *vals,
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unsigned int nregs, unsigned int start_idx);
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u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg);
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struct fw_filter_wr;
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void t4_intr_enable(struct adapter *adapter);
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void t4_intr_disable(struct adapter *adapter);
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void t4_intr_clear(struct adapter *adapter);
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int t4_slow_intr_handler(struct adapter *adapter);
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int t4_hash_mac_addr(const u8 *addr);
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int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
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struct link_config *lc);
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int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
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int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
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int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
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int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
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int t4_seeprom_wp(struct adapter *adapter, int enable);
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int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
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u32 *data, int byte_oriented);
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int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
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int t4_load_boot(struct adapter *adap, u8 *boot_data,
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unsigned int boot_addr, unsigned int size);
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int t4_flash_cfg_addr(struct adapter *adapter);
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int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
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int t4_get_fw_version(struct adapter *adapter, u32 *vers);
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int t4_get_tp_version(struct adapter *adapter, u32 *vers);
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int t4_check_fw_version(struct adapter *adapter);
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int t4_init_hw(struct adapter *adapter, u32 fw_params);
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int t4_prep_adapter(struct adapter *adapter);
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int t4_init_tp_params(struct adapter *adap);
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int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
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int t4_port_init(struct port_info *p, int mbox, int pf, int vf);
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int t4_reinit_adapter(struct adapter *adap);
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void t4_fatal_err(struct adapter *adapter);
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int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
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int filter_index, int enable);
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void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
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int filter_index, int *enabled);
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int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
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int start, int n, const u16 *rspq, unsigned int nrspq);
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int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
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unsigned int flags);
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int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
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unsigned int flags, unsigned int defq);
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int t4_read_rss(struct adapter *adapter, u16 *entries);
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void t4_read_rss_key(struct adapter *adapter, u32 *key);
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void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
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void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp);
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void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val);
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void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
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u32 *vfl, u32 *vfh);
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void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
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u32 vfl, u32 vfh);
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u32 t4_read_rss_pf_map(struct adapter *adapter);
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void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap);
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u32 t4_read_rss_pf_mask(struct adapter *adapter);
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void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask);
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int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
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void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
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void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
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void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
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int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
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int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
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int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
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unsigned int *valp);
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int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
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const unsigned int *valp);
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int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
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unsigned int *valp);
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int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
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void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
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unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
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void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
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int t4_mc_read(struct adapter *adap, int idx, u32 addr,
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__be32 *data, u64 *parity);
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int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
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int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
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__be32 *data);
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void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
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void t4_get_port_stats_offset(struct adapter *adap, int idx,
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struct port_stats *stats,
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struct port_stats *offset);
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void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
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void t4_clr_port_stats(struct adapter *adap, int idx);
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void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
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void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
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void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
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void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
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unsigned int *ipg);
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void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
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unsigned int mask, unsigned int val);
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void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
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void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
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void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st);
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void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
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void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
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void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
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void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
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struct tp_tcp_stats *v6);
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void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
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struct tp_fcoe_stats *st);
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void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
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const unsigned short *alpha, const unsigned short *beta);
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void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
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int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps);
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int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg);
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int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
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unsigned int start, unsigned int n);
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void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
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int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map);
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void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
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void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr);
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int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
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u64 mask0, u64 mask1, unsigned int crc, bool enable);
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int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
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enum dev_master master, enum dev_state *state);
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int t4_fw_bye(struct adapter *adap, unsigned int mbox);
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int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
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int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
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int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
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int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
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const u8 *fw_data, unsigned int size, int force);
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int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
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int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int nparams, const u32 *params,
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u32 *val);
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int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int nparams, const u32 *params,
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const u32 *val);
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int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
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unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
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unsigned int rxqi, unsigned int rxq, unsigned int tc,
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unsigned int vi, unsigned int cmask, unsigned int pmask,
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unsigned int exactf, unsigned int rcaps, unsigned int wxcaps);
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int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
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unsigned int port, unsigned int pf, unsigned int vf,
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unsigned int nmac, u8 *mac, u16 *rss_size,
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unsigned int portfunc, unsigned int idstype);
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int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
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unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
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u16 *rss_size);
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int t4_free_vi(struct adapter *adap, unsigned int mbox,
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unsigned int pf, unsigned int vf,
|
|
unsigned int viid);
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int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
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int mtu, int promisc, int all_multi, int bcast, int vlanex,
|
|
bool sleep_ok);
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int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
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bool free, unsigned int naddr, const u8 **addr, u16 *idx,
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|
u64 *hash, bool sleep_ok);
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int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
int idx, const u8 *addr, bool persist, bool add_smt);
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int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
bool ucast, u64 vec, bool sleep_ok);
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int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
bool rx_en, bool tx_en);
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int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
|
unsigned int nblinks);
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int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
|
|
unsigned int mmd, unsigned int reg, unsigned int *valp);
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int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
|
|
unsigned int mmd, unsigned int reg, unsigned int val);
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int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
|
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int port, unsigned int devid,
|
|
unsigned int offset, unsigned int len,
|
|
u8 *buf);
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|
int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
|
|
int port, unsigned int devid,
|
|
unsigned int offset, unsigned int len,
|
|
u8 *buf);
|
|
int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
|
|
unsigned int pf, unsigned int vf, unsigned int iqid,
|
|
unsigned int fl0id, unsigned int fl1id);
|
|
int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int iqtype, unsigned int iqid,
|
|
unsigned int fl0id, unsigned int fl1id);
|
|
int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int eqid);
|
|
int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int eqid);
|
|
int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
|
unsigned int vf, unsigned int eqid);
|
|
int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
|
|
enum ctxt_type ctype, u32 *data);
|
|
int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
|
|
u32 *data);
|
|
int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
|
|
int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
|
|
int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
|
|
int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
|
|
int sleep_ok);
|
|
int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
|
|
int rateunit, int ratemode, int channel, int cl,
|
|
int minrate, int maxrate, int weight, int pktsize,
|
|
int sleep_ok);
|
|
#endif /* __CHELSIO_COMMON_H */
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