peter 9686d60c61 Add the CR4 values for P3 SIMD enabling support. FXSR tells the cpu that
the OS does FXSAVE/FXRESTOR instructions (fast FPU save/restore) during
context switching and also enables SIMD since this enables saving the
extra CPU context that isn't saved with normal FPU regs.  The other
enables the SIMD instructions to use exception 16 (FPU) error reporting.
Note, this doesn't turn on SIMD, just defines the bits.
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