kato dba64e78dc Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support ... Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is enabled through MSR 0x11e. The L2 cache latency value can be specified by CPU_L2_LATENCY option. Default value of L2 cache latency is 5. These options are useful if you use Socket 8 to Socket 370 converter (e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2 cache of Mendocino Celeron CPUs because they don't know Celeron CPUs. These options are needles if you use a Coppermine (FCPGA) Celeron or PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache is always enabled.		2000-06-13 09:10:37 +00:00
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apm
bios
conf	Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support	2000-06-13 09:10:37 +00:00
i386	Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support	2000-06-13 09:10:37 +00:00
ibcs2	Regenerated (fixed the calculation of sy_nargs in sysent tables).	2000-05-09 21:52:02 +00:00
include	Further fixes for multiple-IO-APIC systems from Tor Egge:	2000-05-31 21:37:28 +00:00
isa	1. Update Comtrol RocketPort driver(rp) to version 3.02.	2000-06-11 06:43:16 +00:00
linux	Back out the previous change to the queue(3) interface.	2000-05-26 02:09:24 +00:00
pci	Add OPTi 82C700 chipset.	2000-05-24 09:03:30 +00:00
svr4	AT&T asm syntax requires a leading '*' in front of the operand for indirect	2000-05-10 01:21:15 +00:00
Makefile