nwhitehorn 990347ec5d Fix interrupt distribution to multiple CPUs on systems with cascaded PICs.
Because slave PICs send all interrupts to their CPU 0 output line (which
is routed to a pin on the master PIC), changes to per-CPU register banks
like EOI on the slave PIC must be accessed for CPU 0, instead of the
CPU actually processing the interrupt.

Submitted by:	Andreas Tobler
2010-07-06 15:31:58 +00:00
..
2010-07-06 10:28:19 +00:00
2010-05-24 16:41:05 +00:00
2010-06-26 13:20:40 +00:00
2010-06-02 17:27:23 +00:00
2010-05-24 16:27:47 +00:00