nwhitehorn 990347ec5d Fix interrupt distribution to multiple CPUs on systems with cascaded PICs. ...

Because slave PICs send all interrupts to their CPU 0 output line (which
is routed to a pin on the master PIC), changes to per-CPU register banks
like EOI on the slave PIC must be accessed for CPU 0, instead of the
CPU actually processing the interrupt.

Submitted by:	Andreas Tobler

2010-07-06 15:31:58 +00:00

..

aim

Remove the unneeded header <machine/intr.h>.

2010-07-02 02:17:39 +00:00

booke

Remove the unneeded header <machine/intr.h>.

2010-07-02 02:17:39 +00:00

compile

…

conf

Change USB_DEBUG to #ifdef and allow it to be turned off. Previously this had

2010-04-22 21:31:34 +00:00

cpufreq

On SMP G5 systems, sometimes the power-mode-data property is only found

2010-05-16 15:21:13 +00:00

fpu

The NetBSD Foundation has granted permission to remove clause 3 and 4 from

2010-03-03 17:07:02 +00:00

include

Remove the unneeded header <machine/intr.h>.

2010-07-02 02:17:39 +00:00

mpc85xx

Move the EOI logic when starting ithreads into intr_machdep instead of

2010-07-06 15:27:05 +00:00

ofw

Add MSI support for PCI devices attached to the CPC925 and CPC945 bridges

2010-06-18 17:39:56 +00:00

powermac

Move the EOI logic when starting ithreads into intr_machdep instead of

2010-07-06 15:27:05 +00:00

powerpc

Fix interrupt distribution to multiple CPUs on systems with cascaded PICs.

2010-07-06 15:31:58 +00:00

psim

Remove the unneeded header <machine/intr.h>.

2010-07-02 02:17:39 +00:00