938c374b23
CPUs. The AR933x is a mips24k based SoC with an AR9380 series SoC on board, two gigabit ethernet interfaces and an internal 10/100mbit ethernet switch. There's also the normal interfaces (USB, ethernet, uart, GPIO.) The downside? There's a non-ns8250 UART device. With a very basic UART driver (not in this commit) the SoC is initialised and boots up. I'll commit the UART code soon and then link it into the general setup path. This code is a re-implementation based from the Linux kernel / openwrt AR933x support. TODO: * UART (obviously) * All of the ethernet, USB and wifi SoC glue, including ethernet PLL programming.
79 lines
3.1 KiB
C
79 lines
3.1 KiB
C
/*-
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* Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __AR93XX_REG_H__
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#define __AR93XX_REG_H__
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#define REV_ID_MAJOR_AR9330 0x0110
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#define REV_ID_MAJOR_AR9331 0x1110
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#define AR933X_REV_ID_REVISION_MASK 0x3
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#define AR933X_GPIO_COUNT 30
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#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR933X_UART_SIZE 0x14
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#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR933X_WMAC_SIZE 0x20000
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#define AR933X_EHCI_BASE 0x1b000000
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#define AR933X_EHCI_SIZE 0x1000
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#define AR933X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x7c)
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#define AR933X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0x80)
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#define AR933X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0x84)
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#define AR933X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0x88)
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#define AR933X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00)
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#define AR933X_PLL_CLOCK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08)
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#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
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#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
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#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
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#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
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#define AR933X_PLL_CLOCK_CTRL_BYPASS (1 << 2)
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#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
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#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
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#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
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#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
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#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
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#define AR933X_RESET_REG_RESET_MODULE (AR71XX_RST_BLOCK_BASE + 0x1c)
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#define AR933X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xac)
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#define AR933X_RESET_WMAC (1 << 11)
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#define AR933X_RESET_USB_HOST (1 << 5)
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#define AR933X_RESET_USB_PHY (1 << 4)
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#define AR933X_RESET_USBSUS_OVERRIDE (1 << 3)
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#define AR933X_BOOTSTRAP_REF_CLK_40 (1 << 0)
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#endif /* __AR93XX_REG_H__ */
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