fad63e2d45
Update the device tree source files to a Linux 4.7-RC. The dts tree currently can't be merged w/o specific revisions. Note: due to a stupid bug in the commit checking script, I couldn't just remove the svn:keyword tag from the new files, I had to add fbsd:nokeywords to all the files (including ones that didn't need it)
1157 lines
30 KiB
Plaintext
1157 lines
30 KiB
Plaintext
/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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/ {
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interrupt-parent = <&gic>;
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aliases {
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ethernet0 = &gmac;
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};
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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simplefb_hdmi: framebuffer@0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0-hdmi";
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clocks = <&pll6 0>;
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status = "disabled";
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};
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simplefb_lcd: framebuffer@1 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&pll6 0>;
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status = "disabled";
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <24000000>;
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arm,cpu-registers-not-fw-configured;
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};
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cpus {
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enable-method = "allwinner,sun6i-a31";
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clocks = <&cpu>;
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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/* kHz uV */
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1008000 1200000
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864000 1200000
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720000 1100000
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480000 1000000
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>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <3>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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};
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};
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thermal-zones {
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cpu_thermal {
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/* milliseconds */
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&rtp>;
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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trips {
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cpu_alert0: cpu_alert0 {
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/* milliCelsius */
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temperature = <70000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit {
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/* milliCelsius */
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temperature = <100000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll6: clk@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6", "pll6x2";
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};
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cpu: cpu@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20050 0x4>;
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/*
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* PLL1 is listed twice here.
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* While it looks suspicious, it's actually documented
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* that way both in the datasheet and in the code from
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* Allwinner.
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*/
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
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clock-output-names = "cpu";
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};
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axi: axi@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-axi-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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ahb1: ahb1@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-ahb1-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
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clock-output-names = "ahb1";
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/*
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* Clock AHB1 from PLL6, instead of CPU/AXI which
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* has rate changes due to cpufreq. Also the DMA
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* controller requires AHB1 clocked from PLL6.
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*/
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assigned-clocks = <&ahb1>;
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assigned-clock-parents = <&pll6 0>;
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};
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ahb1_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb1>;
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clock-indices = <1>, <5>,
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<6>, <8>, <9>,
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<10>, <11>, <12>,
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<13>, <14>,
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<17>, <18>, <19>,
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<20>, <21>, <22>,
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<23>, <24>, <26>,
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<27>, <29>,
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<30>, <31>, <32>,
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<36>, <37>, <40>,
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<43>, <44>, <45>,
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<46>, <47>, <50>,
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<52>, <55>, <56>,
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<57>, <58>;
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clock-output-names = "ahb1_mipidsi", "ahb1_ss",
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"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
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"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
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"ahb1_nand0", "ahb1_sdram",
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"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
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"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
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"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
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"ahb1_ehci1", "ahb1_ohci0",
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"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
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"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
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"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
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"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
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"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
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"ahb1_drc0", "ahb1_drc1";
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};
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apb1: apb1@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1>;
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clock-output-names = "apb1";
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};
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apb1_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-apb1-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb1>;
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clock-indices = <0>, <4>,
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<5>, <12>,
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<13>;
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clock-output-names = "apb1_codec", "apb1_digital_mic",
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"apb1_pio", "apb1_daudio0",
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"apb1_daudio1";
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};
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apb2: clk@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
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clock-output-names = "apb2";
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};
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apb2_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-apb2-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb2>;
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clock-indices = <0>, <1>,
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<2>, <3>, <16>,
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<17>, <18>, <19>,
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<20>, <21>;
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clock-output-names = "apb2_i2c0", "apb2_i2c1",
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"apb2_i2c2", "apb2_i2c3",
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"apb2_uart0", "apb2_uart1",
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"apb2_uart2", "apb2_uart3",
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"apb2_uart4", "apb2_uart5";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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mmc3_clk: clk@01c20094 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20094 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc3",
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"mmc3_output",
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"mmc3_sample";
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};
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ss_clk: clk@01c2009c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c2009c 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "ss";
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};
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spi0_clk: clk@01c200a0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a0 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "spi0";
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};
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spi1_clk: clk@01c200a4 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a4 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "spi1";
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};
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spi2_clk: clk@01c200a8 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a8 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "spi2";
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};
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spi3_clk: clk@01c200ac {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200ac 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "spi3";
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};
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usb_clk: clk@01c200cc {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "allwinner,sun6i-a31-usb-clk";
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reg = <0x01c200cc 0x4>;
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clocks = <&osc24M>;
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clock-indices = <8>, <9>, <10>,
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<16>, <17>,
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<18>;
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clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
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"usb_ohci0", "usb_ohci1",
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"usb_ohci2";
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};
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/*
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* The following two are dummy clocks, placeholders
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* used in the gmac_tx clock. The gmac driver will
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* choose one parent depending on the PHY interface
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* mode, using clk_set_rate auto-reparenting.
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*
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* The actual TX clock rate is not controlled by the
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* gmac_tx clock.
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*/
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mii_phy_tx_clk: clk@1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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clock-output-names = "mii_phy_tx";
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};
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gmac_int_tx_clk: clk@2 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "gmac_int_tx";
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};
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gmac_tx_clk: clk@01c200d0 {
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#clock-cells = <0>;
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compatible = "allwinner,sun7i-a20-gmac-clk";
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reg = <0x01c200d0 0x4>;
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clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
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clock-output-names = "gmac_tx";
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun6i-a31-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 6>;
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resets = <&ahb1_rst 6>;
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#dma-cells = <1>;
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ahb1_gates 8>,
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<&mmc0_clk 0>,
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<&mmc0_clk 1>,
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<&mmc0_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb1_rst 8>;
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|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc1: mmc@01c10000 {
|
|
compatible = "allwinner,sun5i-a13-mmc";
|
|
reg = <0x01c10000 0x1000>;
|
|
clocks = <&ahb1_gates 9>,
|
|
<&mmc1_clk 0>,
|
|
<&mmc1_clk 1>,
|
|
<&mmc1_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ahb1_rst 9>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc2: mmc@01c11000 {
|
|
compatible = "allwinner,sun5i-a13-mmc";
|
|
reg = <0x01c11000 0x1000>;
|
|
clocks = <&ahb1_gates 10>,
|
|
<&mmc2_clk 0>,
|
|
<&mmc2_clk 1>,
|
|
<&mmc2_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ahb1_rst 10>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
mmc3: mmc@01c12000 {
|
|
compatible = "allwinner,sun5i-a13-mmc";
|
|
reg = <0x01c12000 0x1000>;
|
|
clocks = <&ahb1_gates 11>,
|
|
<&mmc3_clk 0>,
|
|
<&mmc3_clk 1>,
|
|
<&mmc3_clk 2>;
|
|
clock-names = "ahb",
|
|
"mmc",
|
|
"output",
|
|
"sample";
|
|
resets = <&ahb1_rst 11>;
|
|
reset-names = "ahb";
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
usb_otg: usb@01c19000 {
|
|
compatible = "allwinner,sun6i-a31-musb";
|
|
reg = <0x01c19000 0x0400>;
|
|
clocks = <&ahb1_gates 24>;
|
|
resets = <&ahb1_rst 24>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "mc";
|
|
phys = <&usbphy 0>;
|
|
phy-names = "usb";
|
|
extcon = <&usbphy 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbphy: phy@01c19400 {
|
|
compatible = "allwinner,sun6i-a31-usb-phy";
|
|
reg = <0x01c19400 0x10>,
|
|
<0x01c1a800 0x4>,
|
|
<0x01c1b800 0x4>;
|
|
reg-names = "phy_ctrl",
|
|
"pmu1",
|
|
"pmu2";
|
|
clocks = <&usb_clk 8>,
|
|
<&usb_clk 9>,
|
|
<&usb_clk 10>;
|
|
clock-names = "usb0_phy",
|
|
"usb1_phy",
|
|
"usb2_phy";
|
|
resets = <&usb_clk 0>,
|
|
<&usb_clk 1>,
|
|
<&usb_clk 2>;
|
|
reset-names = "usb0_reset",
|
|
"usb1_reset",
|
|
"usb2_reset";
|
|
status = "disabled";
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
ehci0: usb@01c1a000 {
|
|
compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
|
|
reg = <0x01c1a000 0x100>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 26>;
|
|
resets = <&ahb1_rst 26>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@01c1a400 {
|
|
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
|
|
reg = <0x01c1a400 0x100>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 29>, <&usb_clk 16>;
|
|
resets = <&ahb1_rst 29>;
|
|
phys = <&usbphy 1>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci1: usb@01c1b000 {
|
|
compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
|
|
reg = <0x01c1b000 0x100>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 27>;
|
|
resets = <&ahb1_rst 27>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci1: usb@01c1b400 {
|
|
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
|
|
reg = <0x01c1b400 0x100>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 30>, <&usb_clk 17>;
|
|
resets = <&ahb1_rst 30>;
|
|
phys = <&usbphy 2>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci2: usb@01c1c400 {
|
|
compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
|
|
reg = <0x01c1c400 0x100>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 31>, <&usb_clk 18>;
|
|
resets = <&ahb1_rst 31>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pio: pinctrl@01c20800 {
|
|
compatible = "allwinner,sun6i-a31-pinctrl";
|
|
reg = <0x01c20800 0x400>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb1_gates 5>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#gpio-cells = <3>;
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
allwinner,pins = "PH20", "PH21";
|
|
allwinner,function = "uart0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
allwinner,pins = "PH14", "PH15";
|
|
allwinner,function = "i2c0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
allwinner,pins = "PH16", "PH17";
|
|
allwinner,function = "i2c1";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
allwinner,pins = "PH18", "PH19";
|
|
allwinner,function = "i2c2";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
allwinner,pins = "PF0", "PF1", "PF2",
|
|
"PF3", "PF4", "PF5";
|
|
allwinner,function = "mmc0";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc1_pins_a: mmc1@0 {
|
|
allwinner,pins = "PG0", "PG1", "PG2", "PG3",
|
|
"PG4", "PG5";
|
|
allwinner,function = "mmc1";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc2_pins_a: mmc2@0 {
|
|
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
|
|
"PC10", "PC11";
|
|
allwinner,function = "mmc2";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
mmc2_8bit_emmc_pins: mmc2@1 {
|
|
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
|
|
"PC10", "PC11", "PC12",
|
|
"PC13", "PC14", "PC15",
|
|
"PC24";
|
|
allwinner,function = "mmc2";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc3_8bit_emmc_pins: mmc3@1 {
|
|
allwinner,pins = "PC6", "PC7", "PC8", "PC9",
|
|
"PC10", "PC11", "PC12",
|
|
"PC13", "PC14", "PC15",
|
|
"PC24";
|
|
allwinner,function = "mmc3";
|
|
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
gmac_pins_mii_a: gmac_mii@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
|
|
"PA8", "PA9", "PA11",
|
|
"PA12", "PA13", "PA14", "PA19",
|
|
"PA20", "PA21", "PA22", "PA23",
|
|
"PA24", "PA26", "PA27";
|
|
allwinner,function = "gmac";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
gmac_pins_gmii_a: gmac_gmii@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
|
|
"PA4", "PA5", "PA6", "PA7",
|
|
"PA8", "PA9", "PA10", "PA11",
|
|
"PA12", "PA13", "PA14", "PA15",
|
|
"PA16", "PA17", "PA18", "PA19",
|
|
"PA20", "PA21", "PA22", "PA23",
|
|
"PA24", "PA25", "PA26", "PA27";
|
|
allwinner,function = "gmac";
|
|
/*
|
|
* data lines in GMII mode run at 125MHz and
|
|
* might need a higher signal drive strength
|
|
*/
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
gmac_pins_rgmii_a: gmac_rgmii@0 {
|
|
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
|
|
"PA9", "PA10", "PA11",
|
|
"PA12", "PA13", "PA14", "PA19",
|
|
"PA20", "PA25", "PA26", "PA27";
|
|
allwinner,function = "gmac";
|
|
/*
|
|
* data lines in RGMII mode use DDR mode
|
|
* and need a higher signal drive strength
|
|
*/
|
|
allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
};
|
|
|
|
ahb1_rst: reset@01c202c0 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-ahb1-reset";
|
|
reg = <0x01c202c0 0xc>;
|
|
};
|
|
|
|
apb1_rst: reset@01c202d0 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
reg = <0x01c202d0 0x4>;
|
|
};
|
|
|
|
apb2_rst: reset@01c202d8 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
reg = <0x01c202d8 0x4>;
|
|
};
|
|
|
|
timer@01c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0xa0>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
wdt1: watchdog@01c20ca0 {
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
reg = <0x01c20ca0 0x20>;
|
|
};
|
|
|
|
lradc: lradc@01c22800 {
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
reg = <0x01c22800 0x100>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtp: rtp@01c25000 {
|
|
compatible = "allwinner,sun6i-a31-ts";
|
|
reg = <0x01c25000 0x100>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
uart0: serial@01c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 16>;
|
|
resets = <&apb2_rst 16>;
|
|
dmas = <&dma 6>, <&dma 6>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@01c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 17>;
|
|
resets = <&apb2_rst 17>;
|
|
dmas = <&dma 7>, <&dma 7>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@01c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 18>;
|
|
resets = <&apb2_rst 18>;
|
|
dmas = <&dma 8>, <&dma 8>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@01c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 19>;
|
|
resets = <&apb2_rst 19>;
|
|
dmas = <&dma 9>, <&dma 9>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@01c29000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29000 0x400>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 20>;
|
|
resets = <&apb2_rst 20>;
|
|
dmas = <&dma 10>, <&dma 10>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@01c29400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c29400 0x400>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&apb2_gates 21>;
|
|
resets = <&apb2_rst 21>;
|
|
dmas = <&dma 22>, <&dma 22>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@01c2ac00 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2ac00 0x400>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb2_gates 0>;
|
|
resets = <&apb2_rst 0>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@01c2b000 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b000 0x400>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb2_gates 1>;
|
|
resets = <&apb2_rst 1>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@01c2b400 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b400 0x400>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb2_gates 2>;
|
|
resets = <&apb2_rst 2>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c3: i2c@01c2b800 {
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
reg = <0x01c2b800 0x400>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb2_gates 3>;
|
|
resets = <&apb2_rst 3>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
gmac: ethernet@01c30000 {
|
|
compatible = "allwinner,sun7i-a20-gmac";
|
|
reg = <0x01c30000 0x1054>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
|
|
clock-names = "stmmaceth", "allwinner_gmac_tx";
|
|
resets = <&ahb1_rst 17>;
|
|
reset-names = "stmmaceth";
|
|
snps,pbl = <2>;
|
|
snps,fixed-burst;
|
|
snps,force_sf_dma_mode;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
crypto: crypto-engine@01c15000 {
|
|
compatible = "allwinner,sun4i-a10-crypto";
|
|
reg = <0x01c15000 0x1000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 5>, <&ss_clk>;
|
|
clock-names = "ahb", "mod";
|
|
resets = <&ahb1_rst 5>;
|
|
reset-names = "ahb";
|
|
};
|
|
|
|
timer@01c60000 {
|
|
compatible = "allwinner,sun6i-a31-hstimer",
|
|
"allwinner,sun7i-a20-hstimer";
|
|
reg = <0x01c60000 0x1000>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 19>;
|
|
resets = <&ahb1_rst 19>;
|
|
};
|
|
|
|
spi0: spi@01c68000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c68000 0x1000>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 20>, <&spi0_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 23>, <&dma 23>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ahb1_rst 20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@01c69000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c69000 0x1000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 21>, <&spi1_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 24>, <&dma 24>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ahb1_rst 21>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@01c6a000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c6a000 0x1000>;
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 22>, <&spi2_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 25>, <&dma 25>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ahb1_rst 22>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@01c6b000 {
|
|
compatible = "allwinner,sun6i-a31-spi";
|
|
reg = <0x01c6b000 0x1000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ahb1_gates 23>, <&spi3_clk>;
|
|
clock-names = "ahb", "mod";
|
|
dmas = <&dma 26>, <&dma 26>;
|
|
dma-names = "rx", "tx";
|
|
resets = <&ahb1_rst 23>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x1000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
rtc: rtc@01f00000 {
|
|
compatible = "allwinner,sun6i-a31-rtc";
|
|
reg = <0x01f00000 0x54>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
nmi_intc: interrupt-controller@01f00c0c {
|
|
compatible = "allwinner,sun6i-a31-sc-nmi";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x01f00c0c 0x38>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
prcm@01f01400 {
|
|
compatible = "allwinner,sun6i-a31-prcm";
|
|
reg = <0x01f01400 0x200>;
|
|
|
|
ar100: ar100_clk {
|
|
compatible = "allwinner,sun6i-a31-ar100-clk";
|
|
#clock-cells = <0>;
|
|
clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
|
|
<&pll6 0>;
|
|
clock-output-names = "ar100";
|
|
};
|
|
|
|
ahb0: ahb0_clk {
|
|
compatible = "fixed-factor-clock";
|
|
#clock-cells = <0>;
|
|
clock-div = <1>;
|
|
clock-mult = <1>;
|
|
clocks = <&ar100>;
|
|
clock-output-names = "ahb0";
|
|
};
|
|
|
|
apb0: apb0_clk {
|
|
compatible = "allwinner,sun6i-a31-apb0-clk";
|
|
#clock-cells = <0>;
|
|
clocks = <&ahb0>;
|
|
clock-output-names = "apb0";
|
|
};
|
|
|
|
apb0_gates: apb0_gates_clk {
|
|
compatible = "allwinner,sun6i-a31-apb0-gates-clk";
|
|
#clock-cells = <1>;
|
|
clocks = <&apb0>;
|
|
clock-output-names = "apb0_pio", "apb0_ir",
|
|
"apb0_timer", "apb0_p2wi",
|
|
"apb0_uart", "apb0_1wire",
|
|
"apb0_i2c";
|
|
};
|
|
|
|
ir_clk: ir_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
clocks = <&osc32k>, <&osc24M>;
|
|
clock-output-names = "ir";
|
|
};
|
|
|
|
apb0_rst: apb0_rst {
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
cpucfg@01f01c00 {
|
|
compatible = "allwinner,sun6i-a31-cpuconfig";
|
|
reg = <0x01f01c00 0x300>;
|
|
};
|
|
|
|
ir: ir@01f02000 {
|
|
compatible = "allwinner,sun5i-a13-ir";
|
|
clocks = <&apb0_gates 1>, <&ir_clk>;
|
|
clock-names = "apb", "ir";
|
|
resets = <&apb0_rst 1>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x01f02000 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
r_pio: pinctrl@01f02c00 {
|
|
compatible = "allwinner,sun6i-a31-r-pinctrl";
|
|
reg = <0x01f02c00 0x400>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 0>;
|
|
resets = <&apb0_rst 0>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#size-cells = <0>;
|
|
#gpio-cells = <3>;
|
|
|
|
ir_pins_a: ir@0 {
|
|
allwinner,pins = "PL4";
|
|
allwinner,function = "s_ir";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
p2wi_pins: p2wi {
|
|
allwinner,pins = "PL0", "PL1";
|
|
allwinner,function = "s_p2wi";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
};
|
|
|
|
p2wi: i2c@01f03400 {
|
|
compatible = "allwinner,sun6i-a31-p2wi";
|
|
reg = <0x01f03400 0x400>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&apb0_gates 3>;
|
|
clock-frequency = <100000>;
|
|
resets = <&apb0_rst 3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&p2wi_pins>;
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|