fad63e2d45
Update the device tree source files to a Linux 4.7-RC. The dts tree currently can't be merged w/o specific revisions. Note: due to a stupid bug in the commit checking script, I couldn't just remove the svn:keyword tag from the new files, I had to add fbsd:nokeywords to all the files (including ones that didn't need it)
372 lines
8.6 KiB
Plaintext
372 lines
8.6 KiB
Plaintext
/*
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* Copyright 2014 Toradex AG
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/ {
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aliases {
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ethernet0 = &fec1;
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ethernet1 = &fec0;
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};
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bl: backlight {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_bl_on>;
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pwms = <&pwm0 0 5000000 0>;
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enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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reg_module_3v3: regulator-module-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "+V3.3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_module_3v3_avdd: regulator-module-3v3-avdd {
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compatible = "regulator-fixed";
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regulator-name = "+V3.3_AVDD_AUDIO";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&adc0 {
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status = "okay";
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vref-supply = <®_module_3v3_avdd>;
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};
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&adc1 {
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status = "okay";
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vref-supply = <®_module_3v3_avdd>;
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};
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&can0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan0>;
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status = "disabled";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "disabled";
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};
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&clks {
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assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
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<&clks VF610_CLK_ENET_TS_SEL>;
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assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
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<&clks VF610_CLK_ENET_50M>;
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};
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&dspi1 {
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bus-num = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dspi1>;
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};
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&edma0 {
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status = "okay";
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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bus-width = <4>;
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cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
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disable-wp;
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};
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&fec1 {
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phy-mode = "rmii";
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phy-supply = <®_module_3v3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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};
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&i2c0 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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};
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&nfc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nfc>;
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status = "okay";
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nand@0 {
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compatible = "fsl,vf610-nfc-nandcs";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <32>;
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nand-ecc-step-size = <2048>;
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nand-on-flash-bbt;
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};
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};
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&pwm0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm0>;
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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};
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&usbdev0 {
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disable-over-current;
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status = "okay";
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};
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&usbh1 {
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disable-over-current;
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status = "okay";
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};
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&usbmisc0 {
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status = "okay";
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};
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&usbmisc1 {
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status = "okay";
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};
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&usbphy0 {
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status = "okay";
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};
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&usbphy1 {
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status = "okay";
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};
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&iomuxc {
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vf610-colibri {
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pinctrl_flexcan0: can0grp {
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fsl,pins = <
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VF610_PAD_PTB14__CAN0_RX 0x31F1
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VF610_PAD_PTB15__CAN0_TX 0x31F2
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>;
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};
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pinctrl_flexcan1: can1grp {
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fsl,pins = <
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VF610_PAD_PTB16__CAN1_RX 0x31F1
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VF610_PAD_PTB17__CAN1_TX 0x31F2
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>;
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};
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pinctrl_gpio_ext: gpio_ext {
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fsl,pins = <
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VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
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VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
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VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
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>;
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};
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pinctrl_dcu0_1: dcu0grp_1 {
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fsl,pins = <
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VF610_PAD_PTE0__DCU0_HSYNC 0x1902
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VF610_PAD_PTE1__DCU0_VSYNC 0x1902
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VF610_PAD_PTE2__DCU0_PCLK 0x1902
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VF610_PAD_PTE4__DCU0_DE 0x1902
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VF610_PAD_PTE5__DCU0_R0 0x1902
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VF610_PAD_PTE6__DCU0_R1 0x1902
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VF610_PAD_PTE7__DCU0_R2 0x1902
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VF610_PAD_PTE8__DCU0_R3 0x1902
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VF610_PAD_PTE9__DCU0_R4 0x1902
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VF610_PAD_PTE10__DCU0_R5 0x1902
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VF610_PAD_PTE11__DCU0_R6 0x1902
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VF610_PAD_PTE12__DCU0_R7 0x1902
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VF610_PAD_PTE13__DCU0_G0 0x1902
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VF610_PAD_PTE14__DCU0_G1 0x1902
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VF610_PAD_PTE15__DCU0_G2 0x1902
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VF610_PAD_PTE16__DCU0_G3 0x1902
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VF610_PAD_PTE17__DCU0_G4 0x1902
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VF610_PAD_PTE18__DCU0_G5 0x1902
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VF610_PAD_PTE19__DCU0_G6 0x1902
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VF610_PAD_PTE20__DCU0_G7 0x1902
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VF610_PAD_PTE21__DCU0_B0 0x1902
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VF610_PAD_PTE22__DCU0_B1 0x1902
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VF610_PAD_PTE23__DCU0_B2 0x1902
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VF610_PAD_PTE24__DCU0_B3 0x1902
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VF610_PAD_PTE25__DCU0_B4 0x1902
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VF610_PAD_PTE26__DCU0_B5 0x1902
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VF610_PAD_PTE27__DCU0_B6 0x1902
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VF610_PAD_PTE28__DCU0_B7 0x1902
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>;
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};
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pinctrl_dspi1: dspi1grp {
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fsl,pins = <
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VF610_PAD_PTD5__DSPI1_CS0 0x33e2
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VF610_PAD_PTD6__DSPI1_SIN 0x33e1
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VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
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VF610_PAD_PTD8__DSPI1_SCK 0x33e2
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>;
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};
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
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VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
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VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
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VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
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VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
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VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
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VF610_PAD_PTB20__GPIO_42 0x219d
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
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VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
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VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
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VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
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VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
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VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
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VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
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VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
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VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
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VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
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>;
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};
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pinctrl_gpio_bl_on: gpio_bl_on {
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fsl,pins = <
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VF610_PAD_PTC0__GPIO_45 0x22ef
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>;
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};
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pinctrl_i2c0: i2c0grp {
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fsl,pins = <
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VF610_PAD_PTB14__I2C0_SCL 0x37ff
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VF610_PAD_PTB15__I2C0_SDA 0x37ff
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>;
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};
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pinctrl_nfc: nfcgrp {
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fsl,pins = <
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VF610_PAD_PTD23__NF_IO7 0x28df
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VF610_PAD_PTD22__NF_IO6 0x28df
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VF610_PAD_PTD21__NF_IO5 0x28df
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VF610_PAD_PTD20__NF_IO4 0x28df
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VF610_PAD_PTD19__NF_IO3 0x28df
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VF610_PAD_PTD18__NF_IO2 0x28df
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VF610_PAD_PTD17__NF_IO1 0x28df
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VF610_PAD_PTD16__NF_IO0 0x28df
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VF610_PAD_PTB24__NF_WE_B 0x28c2
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VF610_PAD_PTB25__NF_CE0_B 0x28c2
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VF610_PAD_PTB27__NF_RE_B 0x28c2
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VF610_PAD_PTC26__NF_RB_B 0x283d
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VF610_PAD_PTC27__NF_ALE 0x28c2
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VF610_PAD_PTC28__NF_CLE 0x28c2
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>;
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};
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pinctrl_pwm0: pwm0grp {
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fsl,pins = <
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VF610_PAD_PTB0__FTM0_CH0 0x1182
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VF610_PAD_PTB1__FTM0_CH1 0x1182
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>;
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};
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pinctrl_pwm1: pwm1grp {
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fsl,pins = <
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VF610_PAD_PTB8__FTM1_CH0 0x1182
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VF610_PAD_PTB9__FTM1_CH1 0x1182
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>;
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};
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pinctrl_uart0: uart0grp {
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fsl,pins = <
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VF610_PAD_PTB10__UART0_TX 0x21a2
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VF610_PAD_PTB11__UART0_RX 0x21a1
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VF610_PAD_PTB12__UART0_RTS 0x21a2
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VF610_PAD_PTB13__UART0_CTS 0x21a1
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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VF610_PAD_PTB4__UART1_TX 0x21a2
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VF610_PAD_PTB5__UART1_RX 0x21a1
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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VF610_PAD_PTD0__UART2_TX 0x21a2
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VF610_PAD_PTD1__UART2_RX 0x21a1
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VF610_PAD_PTD2__UART2_RTS 0x21a2
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VF610_PAD_PTD3__UART2_CTS 0x21a1
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>;
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};
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pinctrl_usbh1_reg: gpio_usb_vbus {
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fsl,pins = <
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VF610_PAD_PTD4__GPIO_83 0x22ed
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>;
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};
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};
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};
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