Adrian Chadd a73d5cc09f arge: do an explicit flush between updating the TX ring and starting transmit. ...

The MIPS busdma sync operations currently are a big no-op on coherent memory.
This isn't strictly correct behaviour as we need a SYNC in here to ensure that
the writes have finished and are visible in main memory before the MMIO accesses
occur.  This will have to be addressed in a later commit.

But, before that happens, let's at least do a flush here to make things
more "correct".

This is required for even remotely sensible behaviour on mips74k with
write-through memory enabled.

2015-10-30 23:07:32 +00:00

..

adm5120

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

alchemy

Fix a typo introduced in r257338.

2013-10-31 02:27:16 +00:00

atheros

arge: do an explicit flush between updating the TX ring and starting transmit.

2015-10-30 23:07:32 +00:00

beri

preload_search_info: make sure mod is set

2015-08-21 15:57:57 +00:00

cavium

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

conf

Commit the right board file - use the right name + hints.

2015-10-22 15:15:45 +00:00

gxemul

Add 32-bit support for Gxemul's oldtestmips machine emulation

2013-09-04 20:34:36 +00:00

idt

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

include

Switch from a stub to a real implementation of pmap_page_set_attr() for mips,

2015-10-21 14:57:59 +00:00

malta

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

mips

mips: use the correct va for wbinv flushing.

2015-10-27 23:11:22 +00:00

nlm

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

rmi

Add domain support to PCI bus allocation

2015-09-16 23:34:51 +00:00

rt305x

Add support for the uart classes to set their default register shift value.

2015-04-11 17:16:23 +00:00

sentry5

Merge from vmobj-rwlock branch:

2013-02-26 01:00:11 +00:00

sibyte

Devices that rely on hints or identify routines for discovery need to

2013-10-29 14:07:31 +00:00