ed3a515759
1. checking whether there's a link before initializing devices on the bus. When there's no link any access onto the bus will wedge the CPU. 2. synthesizing the class & subclass so that the host controller appears as a standard PCI bridge, rather than a PowerPC CPU. |
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.. | ||
atpic.c | ||
ds1553_bus_lbc.c | ||
ds1553_core.c | ||
ds1553_reg.h | ||
i2c.c | ||
isa.c | ||
lbc.c | ||
lbc.h | ||
mpc85xx.c | ||
mpc85xx.h | ||
nexus.c | ||
ocpbus.c | ||
ocpbus.h | ||
opic.c | ||
pci_ocp.c |