c944338750
This machine uses a non-standard scheme to specify the interrupts to be assigned for devices in PCI slots; instead of giving the INO or full interrupt number (which is done for the other devices in this box), the firmware interrupt properties contain intpin numbers, which have to be swizzled as usual on PCI-PCI bridges; however, the PCI host bridge nodes have no interrupt map, so we need to guess the correct INO by slot number of the device or the closest PCI-PCI bridge leading to it, and the intpin. To do this, this fix makes the following changes: - Add a newbus method for sparc64 PCI host bridges to guess the INO, and glue code in ofw_pci_orb_callback() to invoke it based on a new quirk entry. The guessing is only done for interrupt numbers too low to contain any IGN found on e450s. - Create another new quirk entry was created to prevent mapping of EBus interrupts at PCI level; the e450 has full INOs in the interrupt properties of EBus devices, so trying to remap them could cause problems. - Set both quirk entries for e450s; remove the no-swizzle entry. - Determine the psycho half (bus A or B) a driver instance manages in psycho_attach() - Implement the new guessing method for psycho, using the slot number, psycho half and property value (intpin). Thanks go to the testers, especially Brian Denehy, who tested many kernels for me until I had found the right workaround. Tested by: Brian Denehy <B.Denehy@90east.com>, jake, fenner, Marius Strobl <marius@alchemy.franken.de>, Marian Dobre <mari@onix.ro> Approved by: re (scottl)
99 lines
3.0 KiB
C
99 lines
3.0 KiB
C
/*
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* Copyright (c) 1999, 2000 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: psychovar.h,v 1.6 2001/07/20 00:07:13 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _SPARC64_PCI_PSYCHOVAR_H_
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#define _SPARC64_PCI_PSYCHOVAR_H_
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/*
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* per-PCI bus on mainbus softc structure; one for sabre, or two
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* per pair of psycho's.
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*/
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struct psycho_softc {
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device_t sc_dev;
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/*
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* PSYCHO register. we record the base physical address of these
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* also as it is the base of the entire PSYCHO
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*/
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vm_paddr_t sc_basepaddr;
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/* Interrupt Group Number for this device */
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int sc_ign;
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/* our tags (from parent) */
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bus_space_tag_t sc_bustag;
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bus_space_handle_t sc_bushandle;
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bus_dma_tag_t sc_dmatag;
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bus_addr_t sc_pcictl;
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int sc_clockfreq;
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phandle_t sc_node; /* prom node */
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int sc_mode;
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#define PSYCHO_MODE_SABRE 1
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#define PSYCHO_MODE_PSYCHO 2
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/* Bus A or B of a psycho pair? */
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int sc_half;
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struct iommu_state *sc_is;
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u_int32_t sc_dvmabase;
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struct resource *sc_mem_res;
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struct resource *sc_irq_res[6];
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void *sc_ihand[6];
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/*
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* note that the sabre really only has one ranges property,
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* used for both simba a and simba b (but the ranges for
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* real psychos are the same for PCI A and PCI B anyway).
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*/
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struct upa_ranges *sc_range;
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int sc_nrange;
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/* our tags */
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bus_space_tag_t sc_cfgt;
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bus_space_tag_t sc_memt;
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bus_space_tag_t sc_iot;
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bus_dma_tag_t sc_dmat;
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bus_space_handle_t sc_bh[4];
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int sc_busno;
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struct rman sc_mem_rman;
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struct rman sc_io_rman;
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SLIST_ENTRY(psycho_softc) sc_link;
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};
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#endif /* _SPARC64_PCI_PSYCHOVAR_H_ */
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