254 lines
7.0 KiB
C
254 lines
7.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __RK_CRU_H__
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#define __RK_CRU_H__
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_gate.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_link.h>
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#include <arm64/rockchip/clk/rk_clk_armclk.h>
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#include <arm64/rockchip/clk/rk_clk_composite.h>
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#include <arm64/rockchip/clk/rk_clk_fract.h>
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#include <arm64/rockchip/clk/rk_clk_gate.h>
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#include <arm64/rockchip/clk/rk_clk_mux.h>
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#include <arm64/rockchip/clk/rk_clk_pll.h>
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/* Macro for defining various types of clocks. */
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/* Pure gate */
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#define GATE(_idx, _clkname, _pname, _o, _s) \
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{ \
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.id = _idx, \
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.name = _clkname, \
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.parent_name = _pname, \
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.offset = CRU_CLKGATE_CON(_o), \
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.shift = _s, \
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}
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/* Fixed rate clock. */
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#define FRATE(_id, _name, _freq) \
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{ \
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.type = RK_CLK_FIXED, \
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.clk.fixed = &(struct clk_fixed_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = NULL, \
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.clkdef.parent_cnt = 0, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.freq = _freq, \
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}, \
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}
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/* Fixed factor multipier/divider. */
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#define FFACT(_id, _name, _pname, _mult, _div) \
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{ \
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.type = RK_CLK_FIXED, \
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.clk.fixed = &(struct clk_fixed_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.mult = _mult, \
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.div = _div, \
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}, \
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}
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/* Linked clock. */
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#define LINK(_name) \
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{ \
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.type = RK_CLK_LINK, \
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.clk.link = &(struct clk_link_def) { \
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.clkdef.id = 0, \
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.clkdef.name = _name, \
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.clkdef.parent_names = NULL, \
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.clkdef.parent_cnt = 0, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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}, \
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}
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/* Complex clock fo ARM cores. */
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#define ARMDIV(_id, _name, _pn, _r, _o, _ds, _dw, _ms, _mw, _mp, _ap) \
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{ \
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.type = RK_CLK_ARMCLK, \
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.clk.armclk = &(struct rk_clk_armclk_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = _pn, \
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.clkdef.parent_cnt = nitems(_pn), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.muxdiv_offset = CRU_CLKSEL_CON(_o), \
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.mux_shift = _ms, \
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.mux_width = _mw, \
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.div_shift = _ds, \
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.div_width = _dw, \
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.main_parent = _mp, \
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.alt_parent = _ap, \
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.rates = _r, \
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.nrates = nitems(_r), \
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}, \
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}
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/* Fractional rate multipier/divider. */
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#define FRACT(_id, _name, _pname, _f, _o) \
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{ \
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.type = RK_CLK_FRACT, \
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.clk.fract = &(struct rk_clk_fract_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = CRU_CLKSEL_CON(_o), \
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.flags = _f, \
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}, \
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}
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/* Full composite clock. */
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#define COMP(_id, _name, _pnames, _f, _o, _ds, _dw, _ms, _mw) \
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{ \
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.type = RK_CLK_COMPOSITE, \
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.clk.composite = &(struct rk_clk_composite_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = _pnames, \
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.clkdef.parent_cnt = nitems(_pnames), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.muxdiv_offset = CRU_CLKSEL_CON(_o), \
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.mux_shift = _ms, \
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.mux_width = _mw, \
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.div_shift = _ds, \
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.div_width = _dw, \
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | _f, \
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}, \
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}
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/* Composite clock without mux (divider only). */
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#define CDIV(_id, _name, _pname, _f, _o, _ds, _dw) \
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{ \
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.type = RK_CLK_COMPOSITE, \
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.clk.composite = &(struct rk_clk_composite_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = (const char *[]){_pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.muxdiv_offset = CRU_CLKSEL_CON(_o), \
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.div_shift = _ds, \
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.div_width = _dw, \
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.flags = _f, \
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}, \
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}
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/* Complex clock without divider (multiplexer only). */
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#define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \
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{ \
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.type = RK_CLK_MUX, \
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.clk.mux = &(struct rk_clk_mux_def) { \
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.clkdef.id = _id, \
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.clkdef.name = _name, \
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.clkdef.parent_names = _pn, \
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.clkdef.parent_cnt = nitems(_pn), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = CRU_CLKSEL_CON(_mo), \
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.shift = _ms, \
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.width = _mw, \
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.mux_flags = _f, \
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}, \
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}
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struct rk_cru_gate {
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const char *name;
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const char *parent_name;
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uint32_t id;
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uint32_t offset;
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uint32_t shift;
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};
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#define CRU_GATE(idx, clkname, pname, o, s) \
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{ \
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.id = idx, \
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.name = clkname, \
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.parent_name = pname, \
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.offset = o, \
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.shift = s, \
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},
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enum rk_clk_type {
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RK_CLK_UNDEFINED = 0,
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RK3066_CLK_PLL,
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RK3328_CLK_PLL,
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RK3399_CLK_PLL,
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RK_CLK_COMPOSITE,
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RK_CLK_FIXED,
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RK_CLK_FRACT,
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RK_CLK_MUX,
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RK_CLK_ARMCLK,
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RK_CLK_LINK,
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};
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struct rk_clk {
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enum rk_clk_type type;
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union {
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struct rk_clk_pll_def *pll;
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struct rk_clk_composite_def *composite;
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struct rk_clk_mux_def *mux;
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struct rk_clk_armclk_def *armclk;
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struct clk_fixed_def *fixed;
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struct rk_clk_fract_def *fract;
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struct clk_link_def *link;
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} clk;
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};
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struct rk_cru_softc {
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device_t dev;
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struct resource *res;
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struct clkdom *clkdom;
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struct mtx mtx;
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int type;
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uint32_t reset_offset;
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uint32_t reset_num;
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struct rk_cru_gate *gates;
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int ngates;
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struct rk_clk *clks;
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int nclks;
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struct rk_clk_armclk_def *armclk;
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struct rk_clk_armclk_rates *armclk_rates;
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int narmclk_rates;
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};
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DECLARE_CLASS(rk_cru_driver);
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int rk_cru_attach(device_t dev);
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#endif /* __RK_CRU_H__ */
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