1f0387f732
This driver make a special guarantee that "playback" works
on majority hardwares with minimal or without specific vendor
quirk.
This driver is a product of collaborative effort made by:
Stephane E. Potvin <sepotvin@videotron.ca>
Andrea Bittau <a.bittau@cs.ucl.ac.uk>
Wesley Morgan <morganw@chemikals.org>
Daniel Eischen <deischen@FreeBSD.org>
Maxime Guillaud <bsd-ports@mguillaud.net>
Ariff Abdullah <ariff@FreeBSD.org>
....and various people from freebsd-multimedia@FreeBSD.org
Refer to snd_hda(4) for features and issues.
Welcome To HDA.
Sponsored by: Defenxis Sdn. Bhd.
267 lines
11 KiB
C
267 lines
11 KiB
C
/*-
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* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _HDAC_REG_H_
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#define _HDAC_REG_H_
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/****************************************************************************
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* HDA Controller Register Set
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****************************************************************************/
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#define HDAC_GCAP 0x00 /* 2 - Global Capabilities*/
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#define HDAC_VMIN 0x02 /* 1 - Minor Version */
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#define HDAC_VMAJ 0x03 /* 1 - Major Version */
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#define HDAC_OUTPAY 0x04 /* 2 - Output Payload Capability */
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#define HDAC_INPAY 0x06 /* 2 - Input Payload Capability */
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#define HDAC_GCTL 0x08 /* 4 - Global Control */
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#define HDAC_WAKEEN 0x0c /* 2 - Wake Enable */
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#define HDAC_STATESTS 0x0e /* 2 - State Change Status */
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#define HDAC_GSTS 0x10 /* 2 - Global Status */
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#define HDAC_OUTSTRMPAY 0x18 /* 2 - Output Stream Payload Capability */
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#define HDAC_INSTRMPAY 0x1a /* 2 - Input Stream Payload Capability */
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#define HDAC_INTCTL 0x20 /* 4 - Interrupt Control */
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#define HDAC_INTSTS 0x24 /* 4 - Interrupt Status */
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#define HDAC_WALCLK 0x30 /* 4 - Wall Clock Counter */
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#define HDAC_SSYNC 0x38 /* 4 - Stream Synchronization */
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#define HDAC_CORBLBASE 0x40 /* 4 - CORB Lower Base Address */
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#define HDAC_CORBUBASE 0x44 /* 4 - CORB Upper Base Address */
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#define HDAC_CORBWP 0x48 /* 2 - CORB Write Pointer */
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#define HDAC_CORBRP 0x4a /* 2 - CORB Read Pointer */
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#define HDAC_CORBCTL 0x4c /* 1 - CORB Control */
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#define HDAC_CORBSTS 0x4d /* 1 - CORB Status */
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#define HDAC_CORBSIZE 0x4e /* 1 - CORB Size */
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#define HDAC_RIRBLBASE 0x50 /* 4 - RIRB Lower Base Address */
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#define HDAC_RIRBUBASE 0x54 /* 4 - RIRB Upper Base Address */
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#define HDAC_RIRBWP 0x58 /* 2 - RIRB Write Pointer */
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#define HDAC_RINTCNT 0x5a /* 2 - Response Interrupt Count */
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#define HDAC_RIRBCTL 0x5c /* 1 - RIRB Control */
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#define HDAC_RIRBSTS 0x5d /* 1 - RIRB Status */
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#define HDAC_RIRBSIZE 0x5e /* 1 - RIRB Size */
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#define HDAC_ICOI 0x60 /* 4 - Immediate Command Output Interface */
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#define HDAC_ICII 0x64 /* 4 - Immediate Command Input Interface */
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#define HDAC_ICIS 0x68 /* 2 - Immediate Command Status */
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#define HDAC_DPIBLBASE 0x70 /* 4 - DMA Position Buffer Lower Base */
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#define HDAC_DPIBUBASE 0x74 /* 4 - DMA Position Buffer Upper Base */
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#define HDAC_SDCTL0 0x80 /* 3 - Stream Descriptor Control */
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#define HDAC_SDCTL1 0x81 /* 3 - Stream Descriptor Control */
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#define HDAC_SDCTL2 0x82 /* 3 - Stream Descriptor Control */
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#define HDAC_SDSTS 0x83 /* 1 - Stream Descriptor Status */
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#define HDAC_SDLPIB 0x84 /* 4 - Link Position in Buffer */
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#define HDAC_SDCBL 0x88 /* 4 - Cyclic Buffer Length */
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#define HDAC_SDLVI 0x8C /* 2 - Last Valid Index */
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#define HDAC_SDFIFOS 0x90 /* 2 - FIFOS */
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#define HDAC_SDFMT 0x92 /* 2 - fmt */
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#define HDAC_SDBDPL 0x98 /* 4 - Buffer Descriptor Pointer Lower Base */
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#define HDAC_SDBDPU 0x9C /* 4 - Buffer Descriptor Pointer Upper Base */
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#define _HDAC_ISDOFFSET(n, iss, oss) (0x80 + ((n) * 0x20))
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#define _HDAC_ISDCTL(n, iss, oss) (0x00 + _HDAC_ISDOFFSET(n, iss, oss))
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#define _HDAC_ISDSTS(n, iss, oss) (0x03 + _HDAC_ISDOFFSET(n, iss, oss))
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#define _HDAC_ISDPICB(n, iss, oss) (0x04 + _HDAC_ISDOFFSET(n, iss, oss))
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#define _HDAC_ISDCBL(n, iss, oss) (0x08 + _HDAC_ISDOFFSET(n, iss, oss))
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#define _HDAC_ISDLVI(n, iss, oss) (0x0c + _HDAC_ISDOFFSET(n, iss, oss))
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#define _HDAC_ISDFIFOD(n, iss, oss) (0x10 + _HDAC_ISDOFFSET(n, iss, oss))
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#define _HDAC_ISDFMT(n, iss, oss) (0x12 + _HDAC_ISDOFFSET(n, iss, oss))
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#define _HDAC_ISDBDPL(n, iss, oss) (0x18 + _HDAC_ISDOFFSET(n, iss, oss))
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#define _HDAC_ISDBDPU(n, iss, oss) (0x1c + _HDAC_ISDOFFSET(n, iss, oss))
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#define _HDAC_OSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((n) * 0x20))
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#define _HDAC_OSDCTL(n, iss, oss) (0x00 + _HDAC_OSDOFFSET(n, iss, oss))
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#define _HDAC_OSDSTS(n, iss, oss) (0x03 + _HDAC_OSDOFFSET(n, iss, oss))
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#define _HDAC_OSDPICB(n, iss, oss) (0x04 + _HDAC_OSDOFFSET(n, iss, oss))
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#define _HDAC_OSDCBL(n, iss, oss) (0x08 + _HDAC_OSDOFFSET(n, iss, oss))
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#define _HDAC_OSDLVI(n, iss, oss) (0x0c + _HDAC_OSDOFFSET(n, iss, oss))
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#define _HDAC_OSDFIFOD(n, iss, oss) (0x10 + _HDAC_OSDOFFSET(n, iss, oss))
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#define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss))
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#define _HDAC_OSDBDPL(n, iss, oss) (0x18 + _HDAC_OSDOFFSET(n, iss, oss))
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#define _HDAC_OSDBDPU(n, iss, oss) (0x1c + _HDAC_OSDOFFSET(n, iss, oss))
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#define _HDAC_BSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20))
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#define _HDAC_BSDCTL(n, iss, oss) (0x00 + _HDAC_BSDOFFSET(n, iss, oss))
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#define _HDAC_BSDSTS(n, iss, oss) (0x03 + _HDAC_BSDOFFSET(n, iss, oss))
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#define _HDAC_BSDPICB(n, iss, oss) (0x04 + _HDAC_BSDOFFSET(n, iss, oss))
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#define _HDAC_BSDCBL(n, iss, oss) (0x08 + _HDAC_BSDOFFSET(n, iss, oss))
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#define _HDAC_BSDLVI(n, iss, oss) (0x0c + _HDAC_BSDOFFSET(n, iss, oss))
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#define _HDAC_BSDFIFOD(n, iss, oss) (0x10 + _HDAC_BSDOFFSET(n, iss, oss))
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#define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss))
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#define _HDAC_BSDBDPL(n, iss, oss) (0x18 + _HDAC_BSDOFFSET(n, iss, oss))
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#define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss))
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/****************************************************************************
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* HDA Controller Register Fields
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****************************************************************************/
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/* GCAP - Global Capabilities */
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#define HDAC_GCAP_64OK 0x0001
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#define HDAC_GCAP_NSDO_MASK 0x0006
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#define HDAC_GCAP_NSDO_SHIFT 1
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#define HDAC_GCAP_BSS_MASK 0x00f8
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#define HDAC_GCAP_BSS_SHIFT 3
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#define HDAC_GCAP_ISS_MASK 0x0f00
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#define HDAC_GCAP_ISS_SHIFT 8
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#define HDAC_GCAP_OSS_MASK 0xf000
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#define HDAC_GCAP_OSS_SHIFT 12
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#define HDAC_GCAP_NSDO_1SDO 0x00
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#define HDAC_GCAP_NSDO_2SDO 0x02
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#define HDAC_GCAP_NSDO_4SDO 0x04
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#define HDAC_GCAP_BSS(gcap) \
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(((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT)
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#define HDAC_GCAP_ISS(gcap) \
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(((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT)
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#define HDAC_GCAP_OSS(gcap) \
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(((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT)
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/* GCTL - Global Control */
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#define HDAC_GCTL_CRST 0x00000001
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#define HDAC_GCTL_FCNTRL 0x00000002
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#define HDAC_GCTL_UNSOL 0x00000100
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/* WAKEEN - Wake Enable */
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#define HDAC_WAKEEN_SDIWEN_MASK 0x7fff
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#define HDAC_WAKEEN_SDIWEN_SHIFT 0
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/* STATESTS - State Change Status */
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#define HDAC_STATESTS_SDIWAKE_MASK 0x7fff
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#define HDAC_STATESTS_SDIWAKE_SHIFT 0
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#define HDAC_STATESTS_SDIWAKE(statests, n) \
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(((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >> \
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HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001)
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/* GSTS - Global Status */
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#define HDAC_GSTS_FSTS 0x0002
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/* INTCTL - Interrut Control */
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#define HDAC_INTCTL_SIE_MASK 0x3fffffff
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#define HDAC_INTCTL_SIE_SHIFT 0
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#define HDAC_INTCTL_CIE 0x40000000
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#define HDAC_INTCTL_GIE 0x80000000
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/* INTSTS - Interrupt Status */
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#define HDAC_INTSTS_SIS_MASK 0x3fffffff
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#define HDAC_INTSTS_SIS_SHIFT 0
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#define HDAC_INTSTS_CIS 0x40000000
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#define HDAC_INTSTS_GIS 0x80000000
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/* SSYNC - Stream Synchronization */
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#define HDAC_SSYNC_SSYNC_MASK 0x3fffffff
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#define HDAC_SSYNC_SSYNC_SHIFT 0
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/* CORBWP - CORB Write Pointer */
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#define HDAC_CORBWP_CORBWP_MASK 0x00ff
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#define HDAC_CORBWP_CORBWP_SHIFT 0
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/* CORBRP - CORB Read Pointer */
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#define HDAC_CORBRP_CORBRP_MASK 0x00ff
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#define HDAC_CORBRP_CORBRP_SHIFT 0
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#define HDAC_CORBRP_CORBRPRST 0x8000
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/* CORBCTL - CORB Control */
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#define HDAC_CORBCTL_CMEIE 0x01
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#define HDAC_CORBCTL_CORBRUN 0x02
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/* CORBSTS - CORB Status */
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#define HDAC_CORBSTS_CMEI 0x01
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/* CORBSIZE - CORB Size */
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#define HDAC_CORBSIZE_CORBSIZE_MASK 0x03
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#define HDAC_CORBSIZE_CORBSIZE_SHIFT 0
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#define HDAC_CORBSIZE_CORBSZCAP_MASK 0xf0
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#define HDAC_CORBSIZE_CORBSZCAP_SHIFT 4
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#define HDAC_CORBSIZE_CORBSIZE_2 0x00
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#define HDAC_CORBSIZE_CORBSIZE_16 0x01
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#define HDAC_CORBSIZE_CORBSIZE_256 0x02
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#define HDAC_CORBSIZE_CORBSZCAP_2 0x10
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#define HDAC_CORBSIZE_CORBSZCAP_16 0x20
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#define HDAC_CORBSIZE_CORBSZCAP_256 0x40
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#define HDAC_CORBSIZE_CORBSIZE(corbsize) \
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(((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT)
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/* RIRBWP - RIRB Write Pointer */
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#define HDAC_RIRBWP_RIRBWP_MASK 0x00ff
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#define HDAC_RIRBWP_RIRBWP_SHIFT 0
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#define HDAC_RIRBWP_RIRBWPRST 0x8000
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/* RINTCTN - Response Interrupt Count */
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#define HDAC_RINTCNT_MASK 0x00ff
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#define HDAC_RINTCNT_SHIFT 0
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/* RIRBCTL - RIRB Control */
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#define HDAC_RIRBCTL_RINTCTL 0x01
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#define HDAC_RIRBCTL_RIRBDMAEN 0x02
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#define HDAC_RIRBCTL_RIRBOIC 0x04
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/* RIRBSTS - RIRB Status */
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#define HDAC_RIRBSTS_RINTFL 0x01
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#define HDAC_RIRBSTS_RIRBOIS 0x04
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/* RIRBSIZE - RIRB Size */
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#define HDAC_RIRBSIZE_RIRBSIZE_MASK 0x03
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#define HDAC_RIRBSIZE_RIRBSIZE_SHIFT 0
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#define HDAC_RIRBSIZE_RIRBSZCAP_MASK 0xf0
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#define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT 4
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#define HDAC_RIRBSIZE_RIRBSIZE_2 0x00
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#define HDAC_RIRBSIZE_RIRBSIZE_16 0x01
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#define HDAC_RIRBSIZE_RIRBSIZE_256 0x02
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#define HDAC_RIRBSIZE_RIRBSZCAP_2 0x10
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#define HDAC_RIRBSIZE_RIRBSZCAP_16 0x20
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#define HDAC_RIRBSIZE_RIRBSZCAP_256 0x40
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#define HDAC_RIRBSIZE_RIRBSIZE(rirbsize) \
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(((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT)
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/* DPLBASE - DMA Position Lower Base Address */
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#define HDAC_DPLBASE_DPLBASE_MASK 0xffffff80
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#define HDAC_DPLBASE_DPLBASE_SHIFT 7
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#define HDAC_DPLBASE_DPLBASE_DMAPBE 0x00000001
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/* SDCTL - Stream Descriptor Control */
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#define HDAC_SDCTL_SRST 0x000001
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#define HDAC_SDCTL_RUN 0x000002
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#define HDAC_SDCTL_IOCE 0x000004
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#define HDAC_SDCTL_FEIE 0x000008
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#define HDAC_SDCTL_DEIE 0x000010
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#define HDAC_SDCTL_STRIPE_MASK 0x030000
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#define HDAC_SDCTL_STRIPE_SHIFT 16
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#define HDAC_SDCTL_TP 0x040000
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#define HDAC_SDCTL_DIR 0x080000
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#define HDAC_SDCTL2_STRM_MASK 0xf0
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#define HDAC_SDCTL2_STRM_SHIFT 4
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#define HDAC_SDSTS_DESE (1 << 4)
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#define HDAC_SDSTS_FIFOE (1 << 3)
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#define HDAC_SDSTS_BCIS (1 << 2)
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#endif
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