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Mask some LAPIC interrupts

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This commit is contained in:
Ali Mashtizadeh 2014-07-10 12:18:54 -07:00
parent f739b18d4f
commit 6d09e71d9a
2 changed files with 19 additions and 3 deletions
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20
sys/amd64/lapic.c
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@ -22,6 +22,8 @@
#define LAPIC_SIV 0x00F0 /* Spurious Interrupt Vector */
#define LAPIC_SIV_ENABLE 0x100
#define LAPIC_ESR 0x0280 /* Error Status Register */
#define LAPIC_LVT_CMCI 0x02F0 /* LVT CMCI */
#define LAPIC_LVT_TIMER 0x0320 /* LVT Timer */
#define LAPIC_LVT_TIMER_ONESHOT 0x00000000
#define LAPIC_LVT_TIMER_PERIODIC 0x00020000
@ -30,7 +32,9 @@
#define LAPIC_LVT_PMCR 0x0340 /* LVT Performance Monitoring Counter */
#define LAPIC_LVT_LINT0 0x0350 /* LVT LINT0 */
#define LAPIC_LVT_LINT1 0x0360 /* LVT LINT1 */
#define LAPIC_LVT_ERROR 0x0370 /* Error Register */
#define LAPIC_LVT_ERROR 0x0370 /* LVT Error */
#define LAPIC_LVT_FLAG_MASKED 0x00010000 /* Masked */
#define LAPIC_TICR 0x0380 /* Timer Initial Count Register */
#define LAPIC_TCCR 0x0390 /* Timer Currnet Count Register */
#define LAPIC_TDCR 0x03E0 /* Time Divide Configuration Register */
@ -100,13 +104,23 @@ LAPIC_Init()
// Enable interrupts
LAPIC_Write(LAPIC_SIV, LAPIC_SIV_ENABLE | T_IRQ_SPURIOUS);
// Clear any remaining errors
LAPIC_Write(LAPIC_ESR, 0);
// Enable error and thermal interrupts
LAPIC_Write(LAPIC_LVT_ERROR, T_IRQ_ERROR);
LAPIC_Write(LAPIC_LVT_THERMAL, T_IRQ_THERMAL);
// Disable LINT0/1, PMC
LAPIC_Write(LAPIC_LVT_LINT0, LAPIC_LVT_FLAG_MASKED);
LAPIC_Write(LAPIC_LVT_LINT1, LAPIC_LVT_FLAG_MASKED);
LAPIC_Write(LAPIC_LVT_PMCR, LAPIC_LVT_FLAG_MASKED);
LAPIC_Periodic(10000000);
LAPIC_SendEOI();
LAPIC_Write(LAPIC_TPR, 0);
//enable_interrupts();
}

2
sys/amd64/trap.h
View File

@ -32,6 +32,8 @@
#define T_IRQ_KBD (T_IRQ_BASE + 1)
#define T_IRQ_COM1 (T_IRQ_BASE + 4)
#define T_IRQ_SPURIOUS (T_IRQ_BASE + 24)
#define T_IRQ_ERROR (T_IRQ_BASE + 25)
#define T_IRQ_THERMAL (T_IRQ_BASE + 26)
#define T_MAX 64