215 lines
6.7 KiB
C
215 lines
6.7 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2015 Intel Corporation
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*/
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#ifndef _I40E_RXTX_COMMON_AVX_H_
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#define _I40E_RXTX_COMMON_AVX_H_
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#include <stdint.h>
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#include <ethdev_driver.h>
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#include <rte_malloc.h>
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#include "i40e_ethdev.h"
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#include "i40e_rxtx.h"
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#ifndef __INTEL_COMPILER
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#pragma GCC diagnostic ignored "-Wcast-qual"
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#endif
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#ifdef __AVX2__
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static __rte_always_inline void
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i40e_rxq_rearm_common(struct i40e_rx_queue *rxq, __rte_unused bool avx512)
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{
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int i;
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uint16_t rx_id;
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volatile union i40e_rx_desc *rxdp;
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struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
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rxdp = rxq->rx_ring + rxq->rxrearm_start;
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/* Pull 'n' more MBUFs into the software ring */
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if (rte_mempool_get_bulk(rxq->mp,
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(void *)rxep,
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RTE_I40E_RXQ_REARM_THRESH) < 0) {
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if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
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rxq->nb_rx_desc) {
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__m128i dma_addr0;
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dma_addr0 = _mm_setzero_si128();
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for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
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rxep[i].mbuf = &rxq->fake_mbuf;
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_mm_store_si128((__m128i *)&rxdp[i].read,
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dma_addr0);
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}
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}
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rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
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RTE_I40E_RXQ_REARM_THRESH;
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return;
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}
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#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
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struct rte_mbuf *mb0, *mb1;
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__m128i dma_addr0, dma_addr1;
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__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
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RTE_PKTMBUF_HEADROOM);
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/* Initialize the mbufs in vector, process 2 mbufs in one loop */
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for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
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__m128i vaddr0, vaddr1;
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mb0 = rxep[0].mbuf;
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mb1 = rxep[1].mbuf;
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/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
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RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
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offsetof(struct rte_mbuf, buf_addr) + 8);
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vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
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vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
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/* convert pa to dma_addr hdr/data */
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dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
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dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
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/* add headroom to pa values */
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dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
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dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
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/* flush desc with pa dma_addr */
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_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
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_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
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}
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#else
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#ifdef __AVX512VL__
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if (avx512) {
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struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
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struct rte_mbuf *mb4, *mb5, *mb6, *mb7;
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__m512i dma_addr0_3, dma_addr4_7;
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__m512i hdr_room = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
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/* Initialize the mbufs in vector, process 8 mbufs in one loop */
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for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH;
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i += 8, rxep += 8, rxdp += 8) {
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__m128i vaddr0, vaddr1, vaddr2, vaddr3;
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__m128i vaddr4, vaddr5, vaddr6, vaddr7;
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__m256i vaddr0_1, vaddr2_3;
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__m256i vaddr4_5, vaddr6_7;
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__m512i vaddr0_3, vaddr4_7;
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mb0 = rxep[0].mbuf;
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mb1 = rxep[1].mbuf;
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mb2 = rxep[2].mbuf;
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mb3 = rxep[3].mbuf;
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mb4 = rxep[4].mbuf;
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mb5 = rxep[5].mbuf;
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mb6 = rxep[6].mbuf;
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mb7 = rxep[7].mbuf;
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/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
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RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
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offsetof(struct rte_mbuf, buf_addr) + 8);
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vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
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vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
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vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
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vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
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vaddr4 = _mm_loadu_si128((__m128i *)&mb4->buf_addr);
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vaddr5 = _mm_loadu_si128((__m128i *)&mb5->buf_addr);
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vaddr6 = _mm_loadu_si128((__m128i *)&mb6->buf_addr);
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vaddr7 = _mm_loadu_si128((__m128i *)&mb7->buf_addr);
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/**
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* merge 0 & 1, by casting 0 to 256-bit and inserting 1
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* into the high lanes. Similarly for 2 & 3, and so on.
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*/
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vaddr0_1 =
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_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
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vaddr1, 1);
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vaddr2_3 =
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_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
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vaddr3, 1);
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vaddr4_5 =
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_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr4),
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vaddr5, 1);
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vaddr6_7 =
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_mm256_inserti128_si256(_mm256_castsi128_si256(vaddr6),
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vaddr7, 1);
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vaddr0_3 =
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_mm512_inserti64x4(_mm512_castsi256_si512(vaddr0_1),
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vaddr2_3, 1);
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vaddr4_7 =
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_mm512_inserti64x4(_mm512_castsi256_si512(vaddr4_5),
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vaddr6_7, 1);
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/* convert pa to dma_addr hdr/data */
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dma_addr0_3 = _mm512_unpackhi_epi64(vaddr0_3, vaddr0_3);
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dma_addr4_7 = _mm512_unpackhi_epi64(vaddr4_7, vaddr4_7);
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/* add headroom to pa values */
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dma_addr0_3 = _mm512_add_epi64(dma_addr0_3, hdr_room);
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dma_addr4_7 = _mm512_add_epi64(dma_addr4_7, hdr_room);
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/* flush desc with pa dma_addr */
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_mm512_store_si512((__m512i *)&rxdp->read, dma_addr0_3);
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_mm512_store_si512((__m512i *)&(rxdp + 4)->read, dma_addr4_7);
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}
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} else
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#endif /* __AVX512VL__*/
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{
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struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
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__m256i dma_addr0_1, dma_addr2_3;
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__m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
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/* Initialize the mbufs in vector, process 4 mbufs in one loop */
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for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH;
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i += 4, rxep += 4, rxdp += 4) {
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__m128i vaddr0, vaddr1, vaddr2, vaddr3;
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__m256i vaddr0_1, vaddr2_3;
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mb0 = rxep[0].mbuf;
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mb1 = rxep[1].mbuf;
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mb2 = rxep[2].mbuf;
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mb3 = rxep[3].mbuf;
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/* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
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RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
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offsetof(struct rte_mbuf, buf_addr) + 8);
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vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
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vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
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vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
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vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
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/**
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* merge 0 & 1, by casting 0 to 256-bit and inserting 1
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* into the high lanes. Similarly for 2 & 3
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*/
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vaddr0_1 = _mm256_inserti128_si256
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(_mm256_castsi128_si256(vaddr0), vaddr1, 1);
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vaddr2_3 = _mm256_inserti128_si256
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(_mm256_castsi128_si256(vaddr2), vaddr3, 1);
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/* convert pa to dma_addr hdr/data */
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dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
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dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
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/* add headroom to pa values */
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dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
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dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
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/* flush desc with pa dma_addr */
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_mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
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_mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
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}
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}
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#endif
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rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
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if (rxq->rxrearm_start >= rxq->nb_rx_desc)
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rxq->rxrearm_start = 0;
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rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
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rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
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(rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
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/* Update the tail pointer on the NIC */
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I40E_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
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}
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#endif /* __AVX2__*/
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#endif /*_I40E_RXTX_COMMON_AVX_H_*/
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