d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
numam-dpdk/doc/guides/cryptodevs/index.rst

50 lines
1.8 KiB
ReStructuredText
Raw Normal View History

qat: add driver for QuickAssist devices This patch adds a PMD for the Intel Quick Assist Technology DH895xxC hardware accelerator. This patch depends on a QAT PF driver for device initialization. See the file docs/guides/cryptodevs/qat.rst for configuration details This patch supports a limited subset of QAT device functionality, currently supporting chaining of cipher and hash operations for the following algorithmsd: Cipher algorithms: - RTE_CRYPTO_CIPHER_AES_CBC (with 128-bit, 192-bit and 256-bit keys supported) Hash algorithms: - RTE_CRYPTO_AUTH_SHA1_HMAC - RTE_CRYPTO_AUTH_SHA256_HMAC - RTE_CRYPTO_AUTH_SHA512_HMAC - RTE_CRYPTO_AUTH_AES_XCBC_MAC Some limitation on this patchset which shall be contributed in a subsequent release: - Chained mbufs are not supported. - Hash only is not supported. - Cipher only is not supported. - Only in-place is currently supported (destination address is the same as source address). - Only supports session-oriented API implementation (session-less APIs are not supported). Signed-off-by: Declan Doherty <declan.doherty@intel.com> Signed-off-by: John Griffin <john.griffin@intel.com> Signed-off-by: Des O Dea <des.j.o.dea@intel.com> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com> Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
2015-11-25 13:25:14 +00:00
.. BSD LICENSE
crypto/scheduler: add documentation Adds the description of the cryptodev scheduler PMD overview, limitations, build, instructions, modes, etc. Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2017-01-24 16:24:01 +00:00
Copyright(c) 2015 - 2017 Intel Corporation. All rights reserved.
qat: add driver for QuickAssist devices This patch adds a PMD for the Intel Quick Assist Technology DH895xxC hardware accelerator. This patch depends on a QAT PF driver for device initialization. See the file docs/guides/cryptodevs/qat.rst for configuration details This patch supports a limited subset of QAT device functionality, currently supporting chaining of cipher and hash operations for the following algorithmsd: Cipher algorithms: - RTE_CRYPTO_CIPHER_AES_CBC (with 128-bit, 192-bit and 256-bit keys supported) Hash algorithms: - RTE_CRYPTO_AUTH_SHA1_HMAC - RTE_CRYPTO_AUTH_SHA256_HMAC - RTE_CRYPTO_AUTH_SHA512_HMAC - RTE_CRYPTO_AUTH_AES_XCBC_MAC Some limitation on this patchset which shall be contributed in a subsequent release: - Chained mbufs are not supported. - Hash only is not supported. - Cipher only is not supported. - Only in-place is currently supported (destination address is the same as source address). - Only supports session-oriented API implementation (session-less APIs are not supported). Signed-off-by: Declan Doherty <declan.doherty@intel.com> Signed-off-by: John Griffin <john.griffin@intel.com> Signed-off-by: Des O Dea <des.j.o.dea@intel.com> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com> Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
2015-11-25 13:25:14 +00:00
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Crypto Device Drivers
=====================
.. toctree::
:maxdepth: 2
:numbered:
doc: add cryptodevs guide overview Details supported device features and algorithms for each crypto PMD. Signed-off-by: Declan Doherty <declan.doherty@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: John McNamara <john.mcnamara@intel.com>
2016-04-08 17:17:26 +01:00
overview
aesni_mb: add driver for multi buffer based crypto This patch provides the initial implementation of the AES-NI multi-buffer based crypto poll mode driver using DPDK's new cryptodev framework. This PMD is dependent on Intel's multibuffer library, see the whitepaper "Fast Multi-buffer IPsec Implementations on Intel® Architecture Processors", see ref 1 for details on the library's design and ref 2 to download the library itself. This initial implementation is limited to supporting the chained operations of "hash then cipher" or "cipher then hash" for the following cipher and hash algorithms: Cipher algorithms: - RTE_CRYPTO_CIPHER_AES_CBC (with 128-bit, 192-bit and 256-bit keys supported) Authentication algorithms: - RTE_CRYPTO_AUTH_SHA1_HMAC - RTE_CRYPTO_AUTH_SHA256_HMAC - RTE_CRYPTO_AUTH_SHA512_HMAC - RTE_CRYPTO_AUTH_AES_XCBC_MAC Important Note: Due to the fact that the multi-buffer library is designed for accelerating IPsec crypto operation, the digest's generated for the HMAC functions are truncated to lengths specified by IPsec RFC's, ie RFC2404 for using HMAC-SHA-1 with IPsec specifies that the digest is truncate from 20 to 12 bytes. Build instructions: To build DPDK with the AESNI_MB_PMD the user is required to download (ref 2) and compile the multi-buffer library on there system before building DPDK. The environmental variable AESNI_MULTI_BUFFER_LIB_PATH must be exported with the path where you extracted and built the multi buffer library and finally set CONFIG_RTE_LIBRTE_PMD_AESNI_MB=y in config/common_linuxapp. Current status: It's doesn't support crypto operation across chained mbufs, or cipher only or hash only operations. ref 1: https://www-ssl.intel.com/content/www/us/en/intelligent-systems/intel-technology/fast-multi-buffer-ipsec-implementations-ia-processors-p ref 2: https://downloadcenter.intel.com/download/22972 Signed-off-by: Declan Doherty <declan.doherty@intel.com> Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
2015-11-25 13:25:15 +00:00
aesni_mb
aesni_gcm: add driver for AES-GCM crypto operations This patch provides the implementation of an AES-NI accelerated crypto PMD which is dependent on Intel's multi-buffer library, see the white paper "Fast Multi-buffer IPsec Implementations on Intel® Architecture Processors" This PMD supports AES_GCM authenticated encryption and authenticated decryption using 128-bit AES keys The patch also contains the related unit tests functions Signed-off-by: Declan Doherty <declan.doherty@intel.com> Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: John Griffin <john.griffin@intel.com>
2016-03-10 16:41:46 +00:00
aesni_gcm
crypto/armv8: add documentation Add documentation about the driver and update release notes. Signed-off-by: Zbigniew Bodek <zbigniew.bodek@caviumnetworks.com> Reviewed-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
2017-01-18 21:01:58 +01:00
armv8
doc: add NXP DPAA2 SEC Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com> Reviewed-by: Hemant Agrawal <hemant.agrawal@nxp.com> Acked-by: John McNamara <john.mcnamara@intel.com>
2017-04-20 11:14:24 +05:30
dpaa2_sec
crypto/kasumi: add driver for KASUMI library Added new SW PMD which makes use of the libsso_kasumi SW library, which provides wireless algorithms KASUMI F8 and F9 in software. This PMD supports cipher-only, hash-only and chained operations ("cipher then hash" and "hash then cipher") of the following algorithms: - RTE_CRYPTO_SYM_CIPHER_KASUMI_F8 - RTE_CRYPTO_SYM_AUTH_KASUMI_F9 Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
2016-06-20 15:40:04 +01:00
kasumi
crypto/openssl: rename libcrypto to openssl This patch replaces name "libcrypto" to "openssl" from file directories, symbol prefixes and sub-names connected with old name. Renamed poll mode driver files, test files, and documentations. It is done to better name association with library because the cryptography operations are using Openssl library crypto API. Fixes: d61f70b4c918 ("crypto/libcrypto: add driver for OpenSSL library") Signed-off-by: Slawomir Mrozowicz <slawomirx.mrozowicz@intel.com> Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
2016-10-18 13:36:13 +02:00
openssl
null_crypto: add driver for null crypto operations This patch provides the implementation of a NULL crypto PMD, which supports NULL cipher and NULL authentication operations, which can be chained together as follows: - Authentication Only - Cipher Only - Authentication then Cipher - Cipher then Authentication As this is a NULL operation device the crypto operations which are submitted for processing are not actually modified and are stored in a queue pairs processed packets ring ready for collection when rte_cryptodev_burst_dequeue() is called. The patch also contains the related unit tests function to test the PMDs supported operations. Signed-off-by: Declan Doherty <declan.doherty@intel.com> Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
2016-03-11 01:04:10 +00:00
null
crypto/scheduler: add documentation Adds the description of the cryptodev scheduler PMD overview, limitations, build, instructions, modes, etc. Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2017-01-24 16:24:01 +00:00
scheduler
snow3g: add driver for SNOW 3G library Added new SW PMD which makes use of the libsso SW library, which provides wireless algorithms SNOW 3G UEA2 and UIA2 in software. This PMD supports cipher-only, hash-only and chained operations ("cipher then hash" and "hash then cipher") of the following algorithms: - RTE_CRYPTO_SYM_CIPHER_SNOW3G_UEA2 - RTE_CRYPTO_SYM_AUTH_SNOW3G_UIA2 The SNOW 3G hash and cipher algorithms, which are enabled by this crypto PMD are implemented by Intel's libsso software library. For library download and build instructions, see the documentation included (doc/guides/cryptodevs/snow3g.rst) The patch also contains the related unit tests function to test the PMD supported operations. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
2016-03-10 16:33:12 +00:00
snow3g
crypto/kasumi: add driver for KASUMI library Added new SW PMD which makes use of the libsso_kasumi SW library, which provides wireless algorithms KASUMI F8 and F9 in software. This PMD supports cipher-only, hash-only and chained operations ("cipher then hash" and "hash then cipher") of the following algorithms: - RTE_CRYPTO_SYM_CIPHER_KASUMI_F8 - RTE_CRYPTO_SYM_AUTH_KASUMI_F9 Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
2016-06-20 15:40:04 +01:00
qat
crypto/zuc: add driver for ZUC library Added new SW PMD which makes use of the libsso SW library, which provides wireless algorithms ZUC EEA3 and EIA3 in software. This PMD supports cipher-only, hash-only and chained operations ("cipher then hash" and "hash then cipher") of the following algorithms: - RTE_CRYPTO_SYM_CIPHER_ZUC_EEA3 - RTE_CRYPTO_SYM_AUTH_ZUC_EIA3 The ZUC hash and cipher algorithms, which are enabled by this crypto PMD are implemented by Intel's libsso software library. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
2016-09-29 03:59:47 +01:00
zuc
Reference in New Issue Copy Permalink