2017-12-19 15:49:03 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2014 Intel Corporation
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2014-06-04 18:08:31 +00:00
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*/
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#ifndef __INCLUDE_RTE_LRU_H__
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#define __INCLUDE_RTE_LRU_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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2017-12-21 13:00:04 +00:00
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#include <rte_config.h>
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2017-04-28 08:58:30 +00:00
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#ifdef RTE_ARCH_X86_64
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#include "rte_lru_x86.h"
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2017-04-28 08:58:31 +00:00
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#elif defined(RTE_ARCH_ARM64)
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#include "rte_lru_arm64.h"
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2014-06-04 18:08:31 +00:00
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#else
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#undef RTE_TABLE_HASH_LRU_STRATEGY
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#define RTE_TABLE_HASH_LRU_STRATEGY 1
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#endif
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#if RTE_TABLE_HASH_LRU_STRATEGY == 0
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#define lru_init(bucket) \
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do \
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bucket = bucket; \
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while (0)
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#define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU)
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#define lru_update(bucket, mru_val) \
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do { \
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bucket = bucket; \
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mru_val = mru_val; \
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} while (0)
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#elif RTE_TABLE_HASH_LRU_STRATEGY == 1
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#define lru_init(bucket) \
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do \
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bucket->lru_list = 0x0000000100020003LLU; \
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while (0)
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#define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU)
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#define lru_update(bucket, mru_val) \
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do { \
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uint64_t x, pos, x0, x1, x2, mask; \
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\
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x = bucket->lru_list; \
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\
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pos = 4; \
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if ((x >> 48) == ((uint64_t) mru_val)) \
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pos = 3; \
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\
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if (((x >> 32) & 0xFFFFLLU) == ((uint64_t) mru_val)) \
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pos = 2; \
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\
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if (((x >> 16) & 0xFFFFLLU) == ((uint64_t) mru_val)) \
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pos = 1; \
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\
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if ((x & 0xFFFFLLU) == ((uint64_t) mru_val)) \
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pos = 0; \
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\
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\
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pos <<= 4; \
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mask = (~0LLU) << pos; \
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x0 = x & (~mask); \
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x1 = (x >> 16) & mask; \
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x2 = (x << (48 - pos)) & (0xFFFFLLU << 48); \
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x = x0 | x1 | x2; \
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\
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if (pos != 64) \
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bucket->lru_list = x; \
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} while (0)
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2017-04-28 08:58:30 +00:00
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#elif (RTE_TABLE_HASH_LRU_STRATEGY == 2) || (RTE_TABLE_HASH_LRU_STRATEGY == 3)
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2014-06-04 18:08:31 +00:00
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2017-04-28 08:58:30 +00:00
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/**
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* These strategies are implemented in architecture specific header files.
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*/
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2014-06-04 18:08:31 +00:00
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#else
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#error "Incorrect value for RTE_TABLE_HASH_LRU_STRATEGY"
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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