2018-01-10 09:17:10 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
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2014-11-25 17:26:43 +00:00
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* Copyright 2007 Nuova Systems, Inc. All rights reserved.
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*/
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#ifndef _ENIC_H_
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#define _ENIC_H_
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2019-10-23 13:19:27 +00:00
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#include <rte_vxlan.h>
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2020-01-14 00:24:49 +00:00
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#include <rte_ether.h>
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2014-11-25 17:26:43 +00:00
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#include "vnic_enet.h"
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#include "vnic_dev.h"
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2019-09-23 14:41:34 +00:00
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#include "vnic_flowman.h"
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2014-11-25 17:26:43 +00:00
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#include "vnic_wq.h"
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#include "vnic_rq.h"
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#include "vnic_cq.h"
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#include "vnic_intr.h"
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#include "vnic_stats.h"
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#include "vnic_nic.h"
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#include "vnic_rss.h"
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#include "enic_res.h"
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2016-03-04 21:09:00 +00:00
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#include "cq_enet_desc.h"
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2018-04-16 21:49:10 +00:00
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#include <stdbool.h>
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2016-06-23 23:14:58 +00:00
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#include <sys/queue.h>
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#include <rte_spinlock.h>
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2014-11-25 17:26:43 +00:00
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#define DRV_NAME "enic_pmd"
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#define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Poll-mode Driver"
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2015-04-21 05:51:28 +00:00
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#define DRV_COPYRIGHT "Copyright 2008-2015 Cisco Systems, Inc"
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2014-11-25 17:26:43 +00:00
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#define VLAN_ETH_HLEN 18
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#define ENICPMD_SETTING(enic, f) ((enic->config.flags & VENETF_##f) ? 1 : 0)
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#define ENICPMD_BDF_LENGTH 13 /* 0000:00:00.0'\0' */
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#define ENIC_CALC_IP_CKSUM 1
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#define ENIC_CALC_TCP_UDP_CKSUM 2
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#define ENIC_MAX_MTU 9000
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2015-02-17 02:08:08 +00:00
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#define ENIC_PAGE_SIZE 4096
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2014-11-25 17:26:43 +00:00
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#define PAGE_ROUND_UP(x) \
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2015-02-17 02:08:08 +00:00
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((((unsigned long)(x)) + ENIC_PAGE_SIZE-1) & (~(ENIC_PAGE_SIZE-1)))
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2018-10-10 22:11:31 +00:00
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2014-11-25 17:26:43 +00:00
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#define ENICPMD_VFIO_PATH "/dev/vfio/vfio"
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/*#define ENIC_DESC_COUNT_MAKE_ODD (x) do{if ((~(x)) & 1) { (x)--; } }while(0)*/
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#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */
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#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */
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2019-09-05 21:33:17 +00:00
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/* enet SRIOV Standalone vNic VF */
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#define PCI_DEVICE_ID_CISCO_VIC_ENET_SN 0x02B7
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2014-11-25 17:26:43 +00:00
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net/enic: flow API for NICs with advanced filters enabled
Flow support for 1300 series adapters with the 'Advanced Filter'
mode enabled via the UCS management interface. This enables:
Attributes: ingress
Items: Outer eth, ipv4, ipv6, udp, sctp, tcp, vxlan. Inner eth, ipv4,
ipv6, udp, tcp.
Actions: queue, and void
Selectors: 'is', 'spec' and 'mask'. 'last' is not supported
Signed-off-by: John Daley <johndale@cisco.com>
Reviewed-by: Nelson Escobar <neescoba@cisco.com>
2017-05-17 22:38:06 +00:00
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/* Special Filter id for non-specific packet flagging. Don't change value */
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#define ENIC_MAGIC_FILTER_ID 0xffff
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2014-11-25 17:26:43 +00:00
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#define ENICPMD_FDIR_MAX 64
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2018-03-08 02:46:59 +00:00
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/*
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* Interrupt 0: LSC and errors
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* Interrupt 1: rx queue 0
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* Interrupt 2: rx queue 1
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* ...
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*/
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#define ENICPMD_LSC_INTR_OFFSET 0
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#define ENICPMD_RXQ_INTR_OFFSET 1
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2014-11-25 17:26:43 +00:00
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struct enic_fdir_node {
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2015-04-09 09:29:32 +00:00
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struct rte_eth_fdir_filter filter;
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2020-01-14 00:24:50 +00:00
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uint16_t fltr_id;
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uint16_t rq_index;
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2014-11-25 17:26:43 +00:00
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};
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struct enic_fdir {
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2015-04-09 09:29:32 +00:00
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struct rte_eth_fdir_stats stats;
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2014-11-25 17:26:43 +00:00
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struct rte_hash *hash;
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struct enic_fdir_node *nodes[ENICPMD_FDIR_MAX];
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2020-01-14 00:24:50 +00:00
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uint32_t modes;
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uint32_t types_mask;
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2016-09-29 20:56:39 +00:00
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void (*copy_fltr_fn)(struct filter_v2 *filt,
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2019-03-02 10:42:40 +00:00
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const struct rte_eth_fdir_input *input,
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const struct rte_eth_fdir_masks *masks);
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2014-11-25 17:26:43 +00:00
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};
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2016-06-03 00:22:45 +00:00
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struct enic_soft_stats {
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rte_atomic64_t rx_nombuf;
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2016-06-03 00:22:47 +00:00
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rte_atomic64_t rx_packet_errors;
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2017-02-03 01:18:40 +00:00
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rte_atomic64_t tx_oversized;
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2016-06-03 00:22:45 +00:00
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};
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2016-06-23 23:14:58 +00:00
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struct enic_memzone_entry {
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const struct rte_memzone *rz;
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LIST_ENTRY(enic_memzone_entry) entries;
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};
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2019-09-23 14:41:34 +00:00
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/* Defined in enic_fm_flow.c */
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struct enic_flowman;
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struct enic_fm_flow;
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net/enic: flow API for NICs with advanced filters enabled
Flow support for 1300 series adapters with the 'Advanced Filter'
mode enabled via the UCS management interface. This enables:
Attributes: ingress
Items: Outer eth, ipv4, ipv6, udp, sctp, tcp, vxlan. Inner eth, ipv4,
ipv6, udp, tcp.
Actions: queue, and void
Selectors: 'is', 'spec' and 'mask'. 'last' is not supported
Signed-off-by: John Daley <johndale@cisco.com>
Reviewed-by: Nelson Escobar <neescoba@cisco.com>
2017-05-17 22:38:06 +00:00
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struct rte_flow {
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LIST_ENTRY(rte_flow) next;
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2019-09-23 14:41:34 +00:00
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/* Data for filter API based flow (enic_flow.c) */
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uint16_t enic_filter_id;
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net/enic: flow API for NICs with advanced filters enabled
Flow support for 1300 series adapters with the 'Advanced Filter'
mode enabled via the UCS management interface. This enables:
Attributes: ingress
Items: Outer eth, ipv4, ipv6, udp, sctp, tcp, vxlan. Inner eth, ipv4,
ipv6, udp, tcp.
Actions: queue, and void
Selectors: 'is', 'spec' and 'mask'. 'last' is not supported
Signed-off-by: John Daley <johndale@cisco.com>
Reviewed-by: Nelson Escobar <neescoba@cisco.com>
2017-05-17 22:38:06 +00:00
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struct filter_v2 enic_filter;
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2019-09-23 14:41:34 +00:00
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/* Data for flow manager based flow (enic_fm_flow.c) */
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struct enic_fm_flow *fm;
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net/enic: flow API for NICs with advanced filters enabled
Flow support for 1300 series adapters with the 'Advanced Filter'
mode enabled via the UCS management interface. This enables:
Attributes: ingress
Items: Outer eth, ipv4, ipv6, udp, sctp, tcp, vxlan. Inner eth, ipv4,
ipv6, udp, tcp.
Actions: queue, and void
Selectors: 'is', 'spec' and 'mask'. 'last' is not supported
Signed-off-by: John Daley <johndale@cisco.com>
Reviewed-by: Nelson Escobar <neescoba@cisco.com>
2017-05-17 22:38:06 +00:00
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};
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2014-11-25 17:26:43 +00:00
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/* Per-instance private data structure */
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struct enic {
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struct enic *next;
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struct rte_pci_device *pdev;
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struct vnic_enet_config config;
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struct vnic_dev_bar bar0;
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struct vnic_dev *vdev;
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2018-10-03 20:09:28 +00:00
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/*
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* mbuf_initializer contains 64 bits of mbuf rearm_data, used by
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* the avx2 handler at this time.
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*/
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uint64_t mbuf_initializer;
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2015-04-14 14:23:55 +00:00
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unsigned int port_id;
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2018-04-16 21:49:10 +00:00
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bool overlay_offload;
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2014-11-25 17:26:43 +00:00
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struct rte_eth_dev *rte_dev;
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2019-09-06 06:50:20 +00:00
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struct rte_eth_dev_data *dev_data;
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2014-11-25 17:26:43 +00:00
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struct enic_fdir fdir;
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char bdf_name[ENICPMD_BDF_LENGTH];
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int dev_fd;
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int iommu_group_fd;
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int iommu_groupid;
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int eventfd;
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2020-01-14 00:24:49 +00:00
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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2014-11-25 17:26:43 +00:00
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pthread_t err_intr_thread;
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int promisc;
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int allmulti;
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2020-01-14 00:24:50 +00:00
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uint8_t ig_vlan_strip_en;
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2014-11-25 17:26:43 +00:00
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int link_status;
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2020-01-14 00:24:50 +00:00
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uint8_t hw_ip_checksum;
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uint16_t max_mtu;
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uint8_t adv_filters;
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uint32_t flow_filter_mode;
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uint8_t filter_actions; /* HW supported actions */
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2018-04-16 21:49:10 +00:00
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bool vxlan;
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bool disable_overlay; /* devargs disable_overlay=1 */
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2018-10-03 20:09:28 +00:00
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uint8_t enable_avx2_rx; /* devargs enable-avx2-rx=1 */
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2019-09-23 14:41:33 +00:00
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uint8_t geneve_opt_avail; /* Geneve with options offload available */
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uint8_t geneve_opt_enabled; /* Geneve with options offload enabled */
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uint8_t geneve_opt_request; /* devargs geneve-opt=1 */
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2018-06-29 09:29:31 +00:00
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bool nic_cfg_chk; /* NIC_CFG_CHK available */
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bool udp_rss_weak; /* Bodega style UDP RSS */
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2018-06-29 09:29:35 +00:00
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uint8_t ig_vlan_rewrite_mode; /* devargs ig-vlan-rewrite */
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2018-06-29 09:29:36 +00:00
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uint16_t vxlan_port; /* current vxlan port pushed to NIC */
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2019-09-06 06:50:19 +00:00
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int use_simple_tx_handler;
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2014-11-25 17:26:43 +00:00
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unsigned int flags;
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unsigned int priv_flags;
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2018-01-23 01:05:28 +00:00
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/* work queue (len = conf_wq_count) */
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struct vnic_wq *wq;
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unsigned int wq_count; /* equals eth_dev nb_tx_queues */
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2014-11-25 17:26:43 +00:00
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2018-01-23 01:05:28 +00:00
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/* receive queue (len = conf_rq_count) */
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struct vnic_rq *rq;
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unsigned int rq_count; /* equals eth_dev nb_rx_queues */
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2014-11-25 17:26:43 +00:00
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2018-01-23 01:05:28 +00:00
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/* completion queue (len = conf_cq_count) */
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struct vnic_cq *cq;
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unsigned int cq_count; /* equals rq_count + wq_count */
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2014-11-25 17:26:43 +00:00
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2018-03-08 02:46:59 +00:00
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/* interrupt vectors (len = conf_intr_count) */
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struct vnic_intr *intr;
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unsigned int intr_count; /* equals enabled interrupts (lsc + rxqs) */
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2016-06-03 00:22:45 +00:00
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/* software counters */
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struct enic_soft_stats soft_stats;
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2016-06-23 23:14:58 +00:00
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net/enic: fix resource check failures when bonding devices
The enic PMD was using the same variables in the enic structure to
track two different things. Initially rq_count, wq_count, cq_count,
and intr_count were set to the values obtained from the VIC adapters
as the maximum resources allocated on the VIC, then in
enic_set_vnic_res(), they were set to the counts of resources actually
used, discarding the initial values. The checks in enic_set_vnic_res()
were technically incorrect if it is called more than once on a port,
which happens when using bonding, but were harmless in practice as the
checks couldn't fail on the second call.
The enic rx-scatter patch misunderstood the subtleties of
enic_set_vnic_res(), and naively added a multiply by two to the
rq_count check. This resulted in the rq_count check failing when
enic_set_vnic_res() was called a second time, ie when using bonding.
This patch adds new variables to the enic structure to track the
maximum resources the VIC is configured to provide so that the
information isn't later lost and calls to enic_set_vnic_res() do
the expected thing.
Fixes: 856d7ba7ed22 ("net/enic: support scattered Rx")
Signed-off-by: Nelson Escobar <neescoba@cisco.com>
2016-07-06 23:21:59 +00:00
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/* configured resources on vic */
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unsigned int conf_rq_count;
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unsigned int conf_wq_count;
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unsigned int conf_cq_count;
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unsigned int conf_intr_count;
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2016-06-23 23:14:58 +00:00
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/* linked list storing memory allocations */
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LIST_HEAD(enic_memzone_list, enic_memzone_entry) memzone_list;
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rte_spinlock_t memzone_list_lock;
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2016-09-22 17:02:46 +00:00
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rte_spinlock_t mtu_lock;
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2016-06-23 23:14:58 +00:00
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net/enic: flow API for NICs with advanced filters enabled
Flow support for 1300 series adapters with the 'Advanced Filter'
mode enabled via the UCS management interface. This enables:
Attributes: ingress
Items: Outer eth, ipv4, ipv6, udp, sctp, tcp, vxlan. Inner eth, ipv4,
ipv6, udp, tcp.
Actions: queue, and void
Selectors: 'is', 'spec' and 'mask'. 'last' is not supported
Signed-off-by: John Daley <johndale@cisco.com>
Reviewed-by: Nelson Escobar <neescoba@cisco.com>
2017-05-17 22:38:06 +00:00
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LIST_HEAD(enic_flows, rte_flow) flows;
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net/enic: allow to change RSS settings
Currently, when more than 1 receive queues are configured, the driver
always enables RSS with the driver's own default hash type, key, and
RETA. The user is unable to change any of the RSS settings. Address
this by implementing the ethdev RSS API as follows.
Correctly report the RETA size, key size, and supported hash types
through rte_eth_dev_info.
During dev_configure(), initialize RSS according to the device's
mq_mode and rss_conf. Start with the default RETA, and use the default
key unless a custom key is provided.
Add the RETA and rss_conf query/set handlers to let the user change
RSS settings after the initial configuration. The hardware is able to
change hash type, key, and RETA individually. So, the handlers change
only the affected settings.
Refactor/rename several functions in order to make their intentions
clear. For example, remove all traces of RSS from
enicpmd_vlan_offload_set() as it is confusing.
Signed-off-by: Hyong Youb Kim <hyonkim@cisco.com>
Reviewed-by: John Daley <johndale@cisco.com>
2018-03-08 02:46:54 +00:00
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/* RSS */
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uint16_t reta_size;
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uint8_t hash_key_size;
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uint64_t flow_type_rss_offloads; /* 0 indicates RSS not supported */
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/*
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* Keep a copy of current RSS config for queries, as we cannot retrieve
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* it from the NIC.
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*/
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uint8_t rss_hash_type; /* NIC_CFG_RSS_HASH_TYPE flags */
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uint8_t rss_enable;
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uint64_t rss_hf; /* ETH_RSS flags */
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union vnic_rss_key rss_key;
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union vnic_rss_cpu rss_cpu;
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2018-04-16 21:49:10 +00:00
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uint64_t rx_offload_capa; /* DEV_RX_OFFLOAD flags */
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uint64_t tx_offload_capa; /* DEV_TX_OFFLOAD flags */
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2018-06-29 09:29:38 +00:00
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uint64_t tx_queue_offload_capa; /* DEV_TX_OFFLOAD flags */
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2018-04-16 21:49:10 +00:00
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uint64_t tx_offload_mask; /* PKT_TX flags accepted */
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2018-12-10 18:28:55 +00:00
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/* Multicast MAC addresses added to the NIC */
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uint32_t mc_count;
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2019-05-21 16:13:03 +00:00
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struct rte_ether_addr mc_addrs[ENIC_MULTICAST_PERFECT_FILTERS];
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2019-09-23 14:41:34 +00:00
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/* Flow manager API */
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struct enic_flowman *fm;
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2014-11-25 17:26:43 +00:00
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};
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2018-03-08 02:46:55 +00:00
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/* Compute ethdev's max packet size from MTU */
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static inline uint32_t enic_mtu_to_max_rx_pktlen(uint32_t mtu)
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{
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2019-03-14 11:05:32 +00:00
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/* ethdev max size includes eth whereas NIC MTU does not */
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2019-05-21 16:13:05 +00:00
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return mtu + RTE_ETHER_HDR_LEN;
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2018-03-08 02:46:55 +00:00
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}
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2016-10-12 21:12:02 +00:00
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/* Get the CQ index from a Start of Packet(SOP) RQ index */
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static inline unsigned int enic_sop_rq_idx_to_cq_idx(unsigned int sop_idx)
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|
|
|
{
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|
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|
return sop_idx / 2;
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|
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|
}
|
2016-10-12 21:12:03 +00:00
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/* Get the RTE RQ index from a Start of Packet(SOP) RQ index */
|
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static inline unsigned int enic_sop_rq_idx_to_rte_idx(unsigned int sop_idx)
|
2016-09-22 17:02:46 +00:00
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|
|
{
|
2016-10-12 21:12:03 +00:00
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return sop_idx / 2;
|
2016-09-22 17:02:46 +00:00
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}
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2016-10-12 21:12:03 +00:00
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/* Get the Start of Packet(SOP) RQ index from a RTE RQ index */
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static inline unsigned int enic_rte_rq_idx_to_sop_idx(unsigned int rte_idx)
|
2016-06-16 19:19:05 +00:00
|
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|
{
|
2016-10-12 21:12:03 +00:00
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|
return rte_idx * 2;
|
2016-06-16 19:19:05 +00:00
|
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|
}
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|
2016-10-12 21:12:03 +00:00
|
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/* Get the Data RQ index from a RTE RQ index */
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static inline unsigned int enic_rte_rq_idx_to_data_idx(unsigned int rte_idx)
|
2016-06-16 19:19:05 +00:00
|
|
|
{
|
2016-10-12 21:12:03 +00:00
|
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|
return rte_idx * 2 + 1;
|
2016-06-16 19:19:05 +00:00
|
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|
}
|
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static inline unsigned int enic_vnic_rq_count(struct enic *enic)
|
|
|
|
{
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|
return enic->rq_count * 2;
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|
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|
}
|
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|
2014-12-02 13:38:31 +00:00
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static inline unsigned int enic_cq_rq(__rte_unused struct enic *enic, unsigned int rq)
|
2014-11-25 17:26:43 +00:00
|
|
|
{
|
2016-06-28 18:49:11 +00:00
|
|
|
/* Scatter rx uses two receive queues together with one
|
|
|
|
* completion queue, so the completion queue number is no
|
|
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* longer the same as the rq number.
|
|
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|
*/
|
|
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|
return rq / 2;
|
2014-11-25 17:26:43 +00:00
|
|
|
}
|
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static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)
|
|
|
|
{
|
|
|
|
return enic->rq_count + wq;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct enic *pmd_priv(struct rte_eth_dev *eth_dev)
|
|
|
|
{
|
2019-05-29 19:14:58 +00:00
|
|
|
return eth_dev->data->dev_private;
|
2014-11-25 17:26:43 +00:00
|
|
|
}
|
|
|
|
|
2016-06-03 00:22:50 +00:00
|
|
|
static inline uint32_t
|
|
|
|
enic_ring_add(uint32_t n_descriptors, uint32_t i0, uint32_t i1)
|
|
|
|
{
|
|
|
|
uint32_t d = i0 + i1;
|
|
|
|
d -= (d >= n_descriptors) ? n_descriptors : 0;
|
|
|
|
return d;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t
|
|
|
|
enic_ring_sub(uint32_t n_descriptors, uint32_t i0, uint32_t i1)
|
|
|
|
{
|
|
|
|
int32_t d = i1 - i0;
|
|
|
|
return (uint32_t)((d < 0) ? ((int32_t)n_descriptors + d) : d);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint32_t
|
|
|
|
enic_ring_incr(uint32_t n_descriptors, uint32_t idx)
|
|
|
|
{
|
|
|
|
idx++;
|
|
|
|
if (unlikely(idx == n_descriptors))
|
|
|
|
idx = 0;
|
|
|
|
return idx;
|
|
|
|
}
|
|
|
|
|
2019-09-23 14:41:34 +00:00
|
|
|
int dev_is_enic(struct rte_eth_dev *dev);
|
2018-03-08 02:46:53 +00:00
|
|
|
void enic_fdir_stats_get(struct enic *enic,
|
|
|
|
struct rte_eth_fdir_stats *stats);
|
|
|
|
int enic_fdir_add_fltr(struct enic *enic,
|
|
|
|
struct rte_eth_fdir_filter *params);
|
|
|
|
int enic_fdir_del_fltr(struct enic *enic,
|
|
|
|
struct rte_eth_fdir_filter *params);
|
|
|
|
void enic_free_wq(void *txq);
|
|
|
|
int enic_alloc_intr_resources(struct enic *enic);
|
|
|
|
int enic_setup_finish(struct enic *enic);
|
|
|
|
int enic_alloc_wq(struct enic *enic, uint16_t queue_idx,
|
|
|
|
unsigned int socket_id, uint16_t nb_desc);
|
|
|
|
void enic_start_wq(struct enic *enic, uint16_t queue_idx);
|
|
|
|
int enic_stop_wq(struct enic *enic, uint16_t queue_idx);
|
|
|
|
void enic_start_rq(struct enic *enic, uint16_t queue_idx);
|
|
|
|
int enic_stop_rq(struct enic *enic, uint16_t queue_idx);
|
|
|
|
void enic_free_rq(void *rxq);
|
|
|
|
int enic_alloc_rq(struct enic *enic, uint16_t queue_idx,
|
|
|
|
unsigned int socket_id, struct rte_mempool *mp,
|
|
|
|
uint16_t nb_desc, uint16_t free_thresh);
|
|
|
|
int enic_set_vnic_res(struct enic *enic);
|
net/enic: allow to change RSS settings
Currently, when more than 1 receive queues are configured, the driver
always enables RSS with the driver's own default hash type, key, and
RETA. The user is unable to change any of the RSS settings. Address
this by implementing the ethdev RSS API as follows.
Correctly report the RETA size, key size, and supported hash types
through rte_eth_dev_info.
During dev_configure(), initialize RSS according to the device's
mq_mode and rss_conf. Start with the default RETA, and use the default
key unless a custom key is provided.
Add the RETA and rss_conf query/set handlers to let the user change
RSS settings after the initial configuration. The hardware is able to
change hash type, key, and RETA individually. So, the handlers change
only the affected settings.
Refactor/rename several functions in order to make their intentions
clear. For example, remove all traces of RSS from
enicpmd_vlan_offload_set() as it is confusing.
Signed-off-by: Hyong Youb Kim <hyonkim@cisco.com>
Reviewed-by: John Daley <johndale@cisco.com>
2018-03-08 02:46:54 +00:00
|
|
|
int enic_init_rss_nic_cfg(struct enic *enic);
|
|
|
|
int enic_set_rss_conf(struct enic *enic,
|
|
|
|
struct rte_eth_rss_conf *rss_conf);
|
|
|
|
int enic_set_rss_reta(struct enic *enic, union vnic_rss_cpu *rss_cpu);
|
|
|
|
int enic_set_vlan_strip(struct enic *enic);
|
2018-03-08 02:46:53 +00:00
|
|
|
int enic_enable(struct enic *enic);
|
|
|
|
int enic_disable(struct enic *enic);
|
|
|
|
void enic_remove(struct enic *enic);
|
|
|
|
int enic_get_link_status(struct enic *enic);
|
|
|
|
int enic_dev_stats_get(struct enic *enic,
|
|
|
|
struct rte_eth_stats *r_stats);
|
2019-09-06 14:34:54 +00:00
|
|
|
int enic_dev_stats_clear(struct enic *enic);
|
2019-09-14 11:37:24 +00:00
|
|
|
int enic_add_packet_filter(struct enic *enic);
|
2017-05-05 00:40:00 +00:00
|
|
|
int enic_set_mac_address(struct enic *enic, uint8_t *mac_addr);
|
2018-04-16 09:40:17 +00:00
|
|
|
int enic_del_mac_address(struct enic *enic, int mac_index);
|
2018-03-08 02:46:53 +00:00
|
|
|
unsigned int enic_cleanup_wq(struct enic *enic, struct vnic_wq *wq);
|
|
|
|
void enic_send_pkt(struct enic *enic, struct vnic_wq *wq,
|
|
|
|
struct rte_mbuf *tx_pkt, unsigned short len,
|
|
|
|
uint8_t sop, uint8_t eop, uint8_t cq_entry,
|
|
|
|
uint16_t ol_flags, uint16_t vlan_tag);
|
|
|
|
|
|
|
|
void enic_post_wq_index(struct vnic_wq *wq);
|
|
|
|
int enic_probe(struct enic *enic);
|
|
|
|
int enic_clsf_init(struct enic *enic);
|
|
|
|
void enic_clsf_destroy(struct enic *enic);
|
2019-09-23 14:41:34 +00:00
|
|
|
int enic_fm_init(struct enic *enic);
|
|
|
|
void enic_fm_destroy(struct enic *enic);
|
|
|
|
void *enic_alloc_consistent(void *priv, size_t size, dma_addr_t *dma_handle,
|
2020-01-14 00:24:50 +00:00
|
|
|
uint8_t *name);
|
2019-09-23 14:41:34 +00:00
|
|
|
void enic_free_consistent(void *priv, size_t size, void *vaddr,
|
|
|
|
dma_addr_t dma_handle);
|
2016-03-04 21:09:00 +00:00
|
|
|
uint16_t enic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
|
|
uint16_t nb_pkts);
|
2018-06-29 09:29:42 +00:00
|
|
|
uint16_t enic_noscatter_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
|
|
|
|
uint16_t nb_pkts);
|
2017-05-12 10:33:03 +00:00
|
|
|
uint16_t enic_dummy_recv_pkts(void *rx_queue,
|
|
|
|
struct rte_mbuf **rx_pkts,
|
|
|
|
uint16_t nb_pkts);
|
2016-06-03 00:22:49 +00:00
|
|
|
uint16_t enic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
|
2018-03-08 02:46:53 +00:00
|
|
|
uint16_t nb_pkts);
|
2018-06-29 09:29:40 +00:00
|
|
|
uint16_t enic_simple_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
|
|
|
|
uint16_t nb_pkts);
|
2018-01-23 01:05:29 +00:00
|
|
|
uint16_t enic_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
|
|
|
|
uint16_t nb_pkts);
|
2016-06-24 22:29:28 +00:00
|
|
|
int enic_set_mtu(struct enic *enic, uint16_t new_mtu);
|
2019-09-06 06:50:20 +00:00
|
|
|
int enic_link_update(struct rte_eth_dev *eth_dev);
|
2019-09-06 06:50:19 +00:00
|
|
|
bool enic_use_vector_rx_handler(struct rte_eth_dev *eth_dev);
|
|
|
|
void enic_pick_rx_handler(struct rte_eth_dev *eth_dev);
|
|
|
|
void enic_pick_tx_handler(struct rte_eth_dev *eth_dev);
|
2016-09-29 20:56:39 +00:00
|
|
|
void enic_fdir_info(struct enic *enic);
|
|
|
|
void enic_fdir_info_get(struct enic *enic, struct rte_eth_fdir_info *stats);
|
2017-05-17 22:38:05 +00:00
|
|
|
extern const struct rte_flow_ops enic_flow_ops;
|
2019-09-23 14:41:34 +00:00
|
|
|
extern const struct rte_flow_ops enic_fm_flow_ops;
|
2014-11-25 17:26:43 +00:00
|
|
|
#endif /* _ENIC_H_ */
|