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vdpa/mlx5: move DevX CQ creation to common

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Using common function for DevX CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit is contained in:
Michael Baum 2021-01-06 08:19:28 +00:00 committed by Ferruh Yigit
parent 3ddf57069b
commit 0e41abd198
3 changed files with 28 additions and 70 deletions
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10
drivers/vdpa/mlx5/mlx5_vdpa.h
View File

@ -22,6 +22,7 @@
#include <mlx5_glue.h>
#include <mlx5_devx_cmds.h>
#include <mlx5_common_devx.h>
#include <mlx5_prm.h>
@ -46,13 +47,7 @@ struct mlx5_vdpa_cq {
uint32_t armed:1;
int callfd;
rte_spinlock_t sl;
struct mlx5_devx_obj *cq;
struct mlx5dv_devx_umem *umem_obj;
union {
volatile void *umem_buf;
volatile struct mlx5_cqe *cqes;
};
volatile uint32_t *db_rec;
struct mlx5_devx_cq cq_obj;
uint64_t errors;
};
@ -148,7 +143,6 @@ struct mlx5_vdpa_priv {
uint32_t gpa_mkey_index;
struct ibv_mr *null_mr;
struct rte_vhost_memory *vmem;
uint32_t eqn;
struct mlx5dv_devx_event_channel *eventc;
struct mlx5dv_devx_event_channel *err_chnl;
struct mlx5dv_devx_uar *uar;

86
drivers/vdpa/mlx5/mlx5_vdpa_event.c
View File

@ -7,6 +7,7 @@
#include <sys/eventfd.h>
#include <rte_malloc.h>
#include <rte_memory.h>
#include <rte_errno.h>
#include <rte_lcore.h>
#include <rte_atomic.h>
@ -16,6 +17,7 @@
#include <mlx5_common.h>
#include <mlx5_common_os.h>
#include <mlx5_common_devx.h>
#include <mlx5_glue.h>
#include "mlx5_vdpa_utils.h"
@ -48,7 +50,6 @@ mlx5_vdpa_event_qp_global_release(struct mlx5_vdpa_priv *priv)
priv->eventc = NULL;
}
#endif
priv->eqn = 0;
}
/* Prepare all the global resources for all the event objects.*/
@ -59,11 +60,6 @@ mlx5_vdpa_event_qp_global_prepare(struct mlx5_vdpa_priv *priv)
if (priv->eventc)
return 0;
if (mlx5_glue->devx_query_eqn(priv->ctx, 0, &priv->eqn)) {
rte_errno = errno;
DRV_LOG(ERR, "Failed to query EQ number %d.", rte_errno);
return -1;
}
priv->eventc = mlx5_os_devx_create_event_channel(priv->ctx,
MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA);
if (!priv->eventc) {
@ -98,12 +94,7 @@ error:
static void
mlx5_vdpa_cq_destroy(struct mlx5_vdpa_cq *cq)
{
if (cq->cq)
claim_zero(mlx5_devx_cmd_destroy(cq->cq));
if (cq->umem_obj)
claim_zero(mlx5_glue->devx_umem_dereg(cq->umem_obj));
if (cq->umem_buf)
rte_free((void *)(uintptr_t)cq->umem_buf);
mlx5_devx_cq_destroy(&cq->cq_obj);
memset(cq, 0, sizeof(*cq));
}
@ -113,12 +104,12 @@ mlx5_vdpa_cq_arm(struct mlx5_vdpa_priv *priv, struct mlx5_vdpa_cq *cq)
uint32_t arm_sn = cq->arm_sn << MLX5_CQ_SQN_OFFSET;
uint32_t cq_ci = cq->cq_ci & MLX5_CI_MASK;
uint32_t doorbell_hi = arm_sn | MLX5_CQ_DBR_CMD_ALL | cq_ci;
uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq->id;
uint64_t doorbell = ((uint64_t)doorbell_hi << 32) | cq->cq_obj.cq->id;
uint64_t db_be = rte_cpu_to_be_64(doorbell);
uint32_t *addr = RTE_PTR_ADD(priv->uar->base_addr, MLX5_CQ_DOORBELL);
rte_io_wmb();
cq->db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
cq->cq_obj.db_rec[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
rte_wmb();
#ifdef RTE_ARCH_64
*(uint64_t *)addr = db_be;
@ -135,52 +126,25 @@ static int
mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
int callfd, struct mlx5_vdpa_cq *cq)
{
struct mlx5_devx_cq_attr attr = {0};
size_t pgsize = sysconf(_SC_PAGESIZE);
uint32_t umem_size;
struct mlx5_devx_cq_attr attr = {
.use_first_only = 1,
.uar_page_id = priv->uar->page_id,
};
uint16_t event_nums[1] = {0};
uint16_t cq_size = 1 << log_desc_n;
int ret;
cq->log_desc_n = log_desc_n;
umem_size = sizeof(struct mlx5_cqe) * cq_size + sizeof(*cq->db_rec) * 2;
cq->umem_buf = rte_zmalloc(__func__, umem_size, 4096);
if (!cq->umem_buf) {
DRV_LOG(ERR, "Failed to allocate memory for CQ.");
rte_errno = ENOMEM;
return -ENOMEM;
}
cq->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,
(void *)(uintptr_t)cq->umem_buf,
umem_size,
IBV_ACCESS_LOCAL_WRITE);
if (!cq->umem_obj) {
DRV_LOG(ERR, "Failed to register umem for CQ.");
ret = mlx5_devx_cq_create(priv->ctx, &cq->cq_obj, log_desc_n, &attr,
SOCKET_ID_ANY);
if (ret)
goto error;
}
attr.q_umem_valid = 1;
attr.db_umem_valid = 1;
attr.use_first_only = 1;
attr.overrun_ignore = 0;
attr.uar_page_id = priv->uar->page_id;
attr.q_umem_id = cq->umem_obj->umem_id;
attr.q_umem_offset = 0;
attr.db_umem_id = cq->umem_obj->umem_id;
attr.db_umem_offset = sizeof(struct mlx5_cqe) * cq_size;
attr.eqn = priv->eqn;
attr.log_cq_size = log_desc_n;
attr.log_page_size = rte_log2_u32(pgsize);
cq->cq = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
if (!cq->cq)
goto error;
cq->db_rec = RTE_PTR_ADD(cq->umem_buf, (uintptr_t)attr.db_umem_offset);
cq->cq_ci = 0;
cq->log_desc_n = log_desc_n;
rte_spinlock_init(&cq->sl);
/* Subscribe CQ event to the event channel controlled by the driver. */
ret = mlx5_os_devx_subscribe_devx_event(priv->eventc, cq->cq->obj,
sizeof(event_nums),
event_nums,
(uint64_t)(uintptr_t)cq);
ret = mlx5_os_devx_subscribe_devx_event(priv->eventc,
cq->cq_obj.cq->obj,
sizeof(event_nums), event_nums,
(uint64_t)(uintptr_t)cq);
if (ret) {
DRV_LOG(ERR, "Failed to subscribe CQE event.");
rte_errno = errno;
@ -188,8 +152,8 @@ mlx5_vdpa_cq_create(struct mlx5_vdpa_priv *priv, uint16_t log_desc_n,
}
cq->callfd = callfd;
/* Init CQ to ones to be in HW owner in the start. */
cq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;
cq->cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);
cq->cq_obj.cqes[0].op_own = MLX5_CQE_OWNER_MASK;
cq->cq_obj.cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);
/* First arming. */
mlx5_vdpa_cq_arm(priv, cq);
return 0;
@ -216,7 +180,7 @@ mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
uint16_t cur_wqe_counter;
uint16_t comp;
last_word.word = rte_read32(&cq->cqes[0].wqe_counter);
last_word.word = rte_read32(&cq->cq_obj.cqes[0].wqe_counter);
cur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);
comp = cur_wqe_counter + (uint16_t)1 - next_wqe_counter;
if (comp) {
@ -230,7 +194,7 @@ mlx5_vdpa_cq_poll(struct mlx5_vdpa_cq *cq)
cq->errors++;
rte_io_wmb();
/* Ring CQ doorbell record. */
cq->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
rte_io_wmb();
/* Ring SW QP doorbell record. */
eqp->db_rec[0] = rte_cpu_to_be_32(cq->cq_ci + cq_size);
@ -246,7 +210,7 @@ mlx5_vdpa_arm_all_cqs(struct mlx5_vdpa_priv *priv)
for (i = 0; i < priv->nr_virtqs; i++) {
cq = &priv->virtqs[i].eqp.cq;
if (cq->cq && !cq->armed)
if (cq->cq_obj.cq && !cq->armed)
mlx5_vdpa_cq_arm(priv, cq);
}
}
@ -292,7 +256,7 @@ mlx5_vdpa_poll_handle(void *arg)
pthread_mutex_lock(&priv->vq_config_lock);
for (i = 0; i < priv->nr_virtqs; i++) {
cq = &priv->virtqs[i].eqp.cq;
if (cq->cq && !cq->armed) {
if (cq->cq_obj.cq && !cq->armed) {
uint32_t comp = mlx5_vdpa_cq_poll(cq);
if (comp) {
@ -371,7 +335,7 @@ mlx5_vdpa_interrupt_handler(void *cb_arg)
DRV_LOG(DEBUG, "Device %s virtq %d cq %d event was captured."
" Timer is %s, cq ci is %u.\n",
priv->vdev->device->name,
(int)virtq->index, cq->cq->id,
(int)virtq->index, cq->cq_obj.cq->id,
priv->timer_on ? "on" : "off", cq->cq_ci);
cq->armed = 0;
}
@ -702,7 +666,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,
goto error;
}
attr.uar_index = priv->uar->page_id;
attr.cqn = eqp->cq.cq->id;
attr.cqn = eqp->cq.cq_obj.cq->id;
attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));
attr.rq_size = 1 << log_desc_n;
attr.log_rq_stride = rte_log2_u32(MLX5_WSEG_SIZE);

2
drivers/vdpa/mlx5/mlx5_vdpa_virtq.c
View File

@ -500,7 +500,7 @@ mlx5_vdpa_virtq_is_modified(struct mlx5_vdpa_priv *priv,
return -1;
if (vq.size != virtq->vq_size || vq.kickfd != virtq->intr_handle.fd)
return 1;
if (virtq->eqp.cq.cq) {
if (virtq->eqp.cq.cq_obj.cq) {
if (vq.callfd != virtq->eqp.cq.callfd)
return 1;
} else if (vq.callfd != -1) {