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net/sfc/base: move limits config to ef10 NIC board config

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Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
This commit is contained in:
Andy Moreton 2018-02-20 07:34:14 +00:00 committed by Ferruh Yigit
parent 9bd777a7e6
commit 107cf1d792
4 changed files with 11 additions and 36 deletions
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11
drivers/net/sfc/base/ef10_nic.c
View File

@ -1655,6 +1655,17 @@ ef10_nic_board_cfg(
*/
encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
* resources (allocated to this PCIe function), which is zero until
* after we have allocated VIs.
*/
encp->enc_evq_limit = 1024;
encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
encp->enc_buftbl_limit = 0xFFFFFFFF;
/* Get remaining controller-specific board config */
if ((rc = enop->eno_board_cfg(enp)) != 0)

12
drivers/net/sfc/base/hunt_nic.c
View File

@ -205,24 +205,12 @@ hunt_board_cfg(
encp->enc_rx_buf_align_start = 1;
encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
* resources (allocated to this PCIe function), which is zero until
* after we have allocated VIs.
*/
encp->enc_evq_limit = 1024;
encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
/*
* The workaround for bug35388 uses the top bit of transmit queue
* descriptor writes, preventing the use of 4096 descriptor TXQs.
*/
encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
encp->enc_buftbl_limit = 0xFFFFFFFF;
EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;

12
drivers/net/sfc/base/medford2_nic.c
View File

@ -137,16 +137,6 @@ medford2_board_cfg(
}
encp->enc_rx_buf_align_end = end_padding;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
* resources (allocated to this PCIe function), which is zero until
* after we have allocated VIs.
*/
encp->enc_evq_limit = 1024;
encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
/*
* The maximum supported transmit queue size is 2048. TXQs with 4096
* descriptors are not supported as the top bit is used for vfifo
@ -154,8 +144,6 @@ medford2_board_cfg(
*/
encp->enc_txq_max_ndescs = 2048;
encp->enc_buftbl_limit = 0xFFFFFFFF;
EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;

12
drivers/net/sfc/base/medford_nic.c
View File

@ -136,16 +136,6 @@ medford_board_cfg(
}
encp->enc_rx_buf_align_end = end_padding;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
* resources (allocated to this PCIe function), which is zero until
* after we have allocated VIs.
*/
encp->enc_evq_limit = 1024;
encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
/*
* The maximum supported transmit queue size is 2048. TXQs with 4096
* descriptors are not supported as the top bit is used for vfifo
@ -153,8 +143,6 @@ medford_board_cfg(
*/
encp->enc_txq_max_ndescs = 2048;
encp->enc_buftbl_limit = 0xFFFFFFFF;
EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;