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common/cnxk: align NPA stack to ROC cache line size

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Network Pool accelerator (NPA) is part of ROC (Rest Of Chip). So
NPA structures should be aligned to ROC Cache line size and not
CPU cache line size.

Non alignment of NPA stack to ROC cache line will result in
undefined runtime NPA behaviour.

Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
Cc: stable@dpdk.org

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This commit is contained in:
Ashwin Sekhar T K 2021-09-17 16:53:09 +05:30 committed by Jerin Jacob
parent 9eb5cb3b11
commit 14a4e2844b
1 changed files with 1 additions and 1 deletions
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2
drivers/common/cnxk/roc_npa.c
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@ -194,7 +194,7 @@ npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
{
const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
return plt_memzone_reserve_cache_align(mz_name, size);
return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
}
static inline int