net/ipn3ke: add stats register and clearing
ipn3ke can work on 10G mode and 25G mode.
10G mode and 25G mode has different MAC register address for statistics.
This patch implements statistics registers for 10G mode and 25G mode.
Also implements different stats clearing per mode.
Fixes: c01c748e4a ("net/ipn3ke: add new driver")
Cc: stable@dpdk.org
Signed-off-by: Andy Pei <andy.pei@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
This commit is contained in:
Andy Pei
Ferruh Yigit
parent
b15ad79ce9
commit
2171c38eed
@ -273,11 +273,33 @@ ipn3ke_hw_init(struct rte_afu_device *afu_dev,
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/* Enable the RX path */
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ipn3ke_xmac_rx_enable(hw, i, 1);
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/* Clear all TX statistics counters */
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ipn3ke_xmac_tx_clr_stcs(hw, i, 1);
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1);
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/* Clear all RX statistics counters */
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ipn3ke_xmac_rx_clr_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0);
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/* Clear line RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0);
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}
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} else if (hw->retimer.mac_type ==
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IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
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/* Enable inter connect channel */
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for (i = 0; i < hw->port_num; i++) {
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0);
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/* Clear line side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0);
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}
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}
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@ -320,11 +342,32 @@ ipn3ke_hw_uninit(struct ipn3ke_hw *hw)
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/* Disable the RX path */
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ipn3ke_xmac_rx_disable(hw, i, 1);
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/* Clear all TX statistics counters */
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ipn3ke_xmac_tx_clr_stcs(hw, i, 1);
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 1);
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/* Clear all RX statistics counters */
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ipn3ke_xmac_rx_clr_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_10G_stcs(hw, i, 0);
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/* Clear line side RX statistics counters */
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ipn3ke_xmac_rx_clr_10G_stcs(hw, i, 0);
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}
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} else if (hw->retimer.mac_type ==
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IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
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for (i = 0; i < hw->port_num; i++) {
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/* Clear NIC side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 1);
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/* Clear NIC side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 1);
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/* Clear line side TX statistics counters */
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ipn3ke_xmac_tx_clr_25G_stcs(hw, i, 0);
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/* Clear line side RX statistics counters */
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ipn3ke_xmac_rx_clr_25G_stcs(hw, i, 0);
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}
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}
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}
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@ -654,239 +654,298 @@ ipn3ke_tm_ops_get(struct rte_eth_dev *ethdev,
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#define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \
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IPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT)
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#define IPN3KE_MAC_TX_STATS_CLR 0x0140
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#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT 0
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#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK \
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IPN3KE_MASK(0x1, IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT)
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#define IPN3KE_REGISTER_WIDTH 32
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#define IPN3KE_MAC_RX_STATS_CLR 0x01C0
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#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT 0
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#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK \
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IPN3KE_MASK(0x1, IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT)
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/*Bits[2:0]: Configuration of TX statistics counters:
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*Bit[2]: Shadow request (active high): When set to the value of 1,
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*TX statistics collection is paused. The underlying counters
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*continue to operate, but the readable values reflect a snapshot at
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*the time the pause flag was activated. Write a 0 to release.
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*Bit[1]: Parity-error clear. When software sets this bit, the IP core
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*clears the parity bit CNTR_TX_STATUS[0]. This bit
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*(CNTR_TX_CONFIG[1]) is self-clearing.
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*Bit[0]: Software can set this bit to the value of 1 to reset all of
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*the TX statistics registers at the same time. This bit is selfclearing.
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*Bits[31:3] are Reserved
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*/
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#define IPN3KE_25G_TX_STATISTICS_CONFIG 0x845
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#define IPN3KE_25G_TX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK 0x00000004
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/*tx_stats_framesOK*/
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#define IPN3KE_MAC_TX_STATS_FRAMESOK_HI 0x0142
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#define IPN3KE_MAC_TX_STATS_FRAMESOK_LOW 0x0143
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/*Bit[1]: Indicates that the TX statistics registers are paused (while
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*CNTR_TX_CONFIG[2] is asserted).
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*Bit[0]: Indicates the presence of at least one parity error in the
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*TX statistics counters.
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*Bits[31:2] are Reserved.
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*/
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#define IPN3KE_25G_TX_STATISTICS_STATUS 0x846
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#define IPN3KE_25G_TX_STATISTICS_STATUS_SHADOW_REQUEST_MASK 0x00000002
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/*rx_stats_framesOK*/
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#define IPN3KE_MAC_RX_STATS_FRAMESOK_HI 0x01C2
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#define IPN3KE_MAC_RX_STATS_FRAMESOK_LOW 0x01C3
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#define IPN3KE_25G_CNTR_TX_FRAGMENTS_LO 0x800
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#define IPN3KE_25G_CNTR_TX_FRAGMENTS_HI 0x801
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#define IPN3KE_25G_CNTR_TX_JABBERS_LO 0x802
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#define IPN3KE_25G_CNTR_TX_JABBERS_HI 0x803
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#define IPN3KE_25G_CNTR_TX_FCS_LO 0x804
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#define IPN3KE_25G_CNTR_TX_FCS_HI 0x805
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#define IPN3KE_25G_CNTR_TX_CRCERR_LO 0x806
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#define IPN3KE_25G_CNTR_TX_CRCERR_HI 0x807
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#define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_LO 0x808
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#define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_HI 0x809
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#define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_LO 0x80A
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#define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_HI 0x80B
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#define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_LO 0x80C
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#define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_HI 0x80D
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#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_LO 0x80E
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#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_HI 0x80F
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#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_LO 0x810
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#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_HI 0x811
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#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_LO 0x812
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#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_HI 0x813
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#define IPN3KE_25G_CNTR_TX_PAUSE_ERR_LO 0x814
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#define IPN3KE_25G_CNTR_TX_PAUSE_ERR_HI 0x815
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#define IPN3KE_25G_CNTR_TX_64B_LO 0x816
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#define IPN3KE_25G_CNTR_TX_64B_HI 0x817
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#define IPN3KE_25G_CNTR_TX_65_127B_LO 0x818
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#define IPN3KE_25G_CNTR_TX_65_127B_HI 0x819
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#define IPN3KE_25G_CNTR_TX_128_255B_LO 0x81A
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#define IPN3KE_25G_CNTR_TX_128_255B_HI 0x81B
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#define IPN3KE_25G_CNTR_TX_256_511B_LO 0x81C
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#define IPN3KE_25G_CNTR_TX_256_511B_HI 0x81D
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#define IPN3KE_25G_CNTR_TX_512_1023B_LO 0x81E
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#define IPN3KE_25G_CNTR_TX_512_1023B_HI 0x81F
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#define IPN3KE_25G_CNTR_TX_1024_1518B_LO 0x820
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#define IPN3KE_25G_CNTR_TX_1024_1518B_HI 0x821
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#define IPN3KE_25G_CNTR_TX_1519_MAXB_LO 0x822
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#define IPN3KE_25G_CNTR_TX_1519_MAXB_HI 0x823
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#define IPN3KE_25G_CNTR_TX_OVERSIZE_LO 0x824
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#define IPN3KE_25G_CNTR_TX_OVERSIZE_HI 0x825
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#define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_LO 0x826
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#define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_HI 0x827
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#define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_LO 0x828
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#define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_HI 0x829
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#define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_LO 0x82A
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#define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_HI 0x82B
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#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_LO 0x82C
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#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_HI 0x82D
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#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_LO 0x82E
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#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_HI 0x82F
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#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_LO 0x830
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#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_HI 0x831
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#define IPN3KE_25G_CNTR_TX_PAUSE_LO 0x832
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#define IPN3KE_25G_CNTR_TX_PAUSE_HI 0x833
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#define IPN3KE_25G_CNTR_TX_RUNT_LO 0x834
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#define IPN3KE_25G_CNTR_TX_RUNT_HI 0x835
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#define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_LO 0x860
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#define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_HI 0x861
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#define IPN3KE_25G_TX_FRAME_OCTETS_OK_LO 0x862
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#define IPN3KE_25G_TX_FRAME_OCTETS_OK_HI 0x863
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/*tx_stats_framesErr*/
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#define IPN3KE_MAC_TX_STATS_FRAMESERR_HI 0x0144
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#define IPN3KE_MAC_TX_STATS_FRAMESERR_LOW 0x0145
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/*Bits[2:0]: Configuration of RX statistics counters:
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*Bit[2]: Shadow request (active high): When set to the value of 1,
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*RX statistics collection is paused. The underlying counters
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*continue to operate, but the readable values reflect a snapshot
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*at the time the pause flag was activated. Write a 0 to release.
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*Bit[1]: Parity-error clear. When software sets this bit, the IP
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*core clears the parity bit CNTR_RX_STATUS[0]. This bit
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*(CNTR_RX_CONFIG[1]) is self-clearing.
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*Bit[0]: Software can set this bit to the value of 1 to reset all of
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*the RX statistics registers at the same time. This bit is selfclearing.
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*Bits[31:3] are Reserved.
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*/
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#define IPN3KE_25G_RX_STATISTICS_CONFIG 0x945
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#define IPN3KE_25G_RX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK 0x00000004
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/*rx_stats_framesErr*/
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#define IPN3KE_MAC_RX_STATS_FRAMESERR_HI 0x01C4
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#define IPN3KE_MAC_RX_STATS_FRAMESERR_LOW 0x01C5
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/*Bit[1]: Indicates that the RX statistics registers are paused
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*(while CNTR_RX_CONFIG[2] is asserted).
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*Bit[0]: Indicates the presence of at least one parity error in the
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*RX statistics counters.
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*Bits [31:2] are Reserved
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*/
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#define IPN3KE_25G_RX_STATISTICS_STATUS 0x946
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#define IPN3KE_25G_RX_STATISTICS_STATUS_SHADOW_REQUEST_MASK 0x00000002
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/*rx_stats_framesCRCErr*/
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#define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_HI 0x01C6
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#define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_LOW 0x01C7
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#define IPN3KE_25G_CNTR_RX_FRAGMENTS_LO 0x900
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#define IPN3KE_25G_CNTR_RX_FRAGMENTS_HI 0x901
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#define IPN3KE_25G_CNTR_RX_JABBERS_LO 0x902
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#define IPN3KE_25G_CNTR_RX_JABBERS_HI 0x903
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#define IPN3KE_25G_CNTR_RX_FCS_LO 0x904
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#define IPN3KE_25G_CNTR_RX_FCS_HI 0x905
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#define IPN3KE_25G_CNTR_RX_CRCERR_LO 0x906
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#define IPN3KE_25G_CNTR_RX_CRCERR_HI 0x907
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#define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_LO 0x908
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#define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_HI 0x909
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#define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_LO 0x90A
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#define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_HI 0x90B
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#define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_LO 0x90C
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#define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_HI 0x90D
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#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_LO 0x90E
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#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_HI 0x90F
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#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_LO 0x910
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#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_HI 0x911
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#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_LO 0x912
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#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_HI 0x913
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#define IPN3KE_25G_CNTR_RX_PAUSE_ERR_LO 0x914
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#define IPN3KE_25G_CNTR_RX_PAUSE_ERR_HI 0x915
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#define IPN3KE_25G_CNTR_RX_64B_LO 0x916
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#define IPN3KE_25G_CNTR_RX_64B_HI 0x917
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#define IPN3KE_25G_CNTR_RX_65_127B_LO 0x918
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#define IPN3KE_25G_CNTR_RX_65_127B_HI 0x919
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#define IPN3KE_25G_CNTR_RX_128_255B_LO 0x91A
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#define IPN3KE_25G_CNTR_RX_128_255B_HI 0x91B
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#define IPN3KE_25G_CNTR_RX_256_511B_LO 0x91C
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#define IPN3KE_25G_CNTR_RX_256_511B_HI 0x91D
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#define IPN3KE_25G_CNTR_RX_512_1023B_LO 0x91E
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#define IPN3KE_25G_CNTR_RX_512_1023B_HI 0x91F
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#define IPN3KE_25G_CNTR_RX_1024_1518B_LO 0x920
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#define IPN3KE_25G_CNTR_RX_1024_1518B_HI 0x921
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#define IPN3KE_25G_CNTR_RX_1519_MAXB_LO 0x922
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#define IPN3KE_25G_CNTR_RX_1519_MAXB_HI 0x923
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#define IPN3KE_25G_CNTR_RX_OVERSIZE_LO 0x924
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#define IPN3KE_25G_CNTR_RX_OVERSIZE_HI 0x925
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#define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_LO 0x926
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#define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_HI 0x927
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#define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_LO 0x928
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#define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_HI 0x929
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#define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_LO 0x92A
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#define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_HI 0x92B
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#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_LO 0x92C
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#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_HI 0x92D
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#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_LO 0x92E
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#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_HI 0x92F
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#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_LO 0x930
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#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_HI 0x931
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#define IPN3KE_25G_CNTR_RX_PAUSE_LO 0x932
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#define IPN3KE_25G_CNTR_RX_PAUSE_HI 0x933
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#define IPN3KE_25G_CNTR_RX_RUNT_LO 0x934
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#define IPN3KE_25G_CNTR_RX_RUNT_HI 0x935
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#define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_LO 0x960
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#define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_HI 0x961
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#define IPN3KE_25G_RX_FRAME_OCTETS_OK_LO 0x962
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#define IPN3KE_25G_RX_FRAME_OCTETS_OK_HI 0x963
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/*tx_stats_octetsOK 64b*/
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#define IPN3KE_MAC_TX_STATS_OCTETSOK_HI 0x0148
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#define IPN3KE_MAC_TX_STATS_OCTETSOK_LOW 0x0149
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#define IPN3KE_10G_STATS_HI_VALID_MASK 0x0000000F
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/*rx_stats_octetsOK 64b*/
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#define IPN3KE_MAC_RX_STATS_OCTETSOK_HI 0x01C8
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#define IPN3KE_MAC_RX_STATS_OCTETSOK_LOW 0x01C9
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#define IPN3KE_10G_TX_STATS_CLR 0x0140
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#define IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT 0
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#define IPN3KE_10G_TX_STATS_CLR_CLEAR_MASK \
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IPN3KE_MASK(0x1, IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT)
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/*tx_stats_pauseMACCtrl_Frames*/
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#define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_HI 0x014A
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#define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x014B
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#define IPN3KE_10G_RX_STATS_CLR 0x01C0
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#define IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT 0
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#define IPN3KE_10G_RX_STATS_CLR_CLEAR_MASK \
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IPN3KE_MASK(0x1, IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT)
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/*rx_stats_pauseMACCtrl_Frames*/
|
||||
#define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_HI 0x01CA
|
||||
#define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x01CB
|
||||
|
||||
/*tx_stats_ifErrors*/
|
||||
#define IPN3KE_MAC_TX_STATS_IFERRORS_HI 0x014C
|
||||
#define IPN3KE_MAC_TX_STATS_IFERRORS_LOW 0x014D
|
||||
|
||||
/*rx_stats_ifErrors*/
|
||||
#define IPN3KE_MAC_RX_STATS_IFERRORS_HI 0x01CC
|
||||
#define IPN3KE_MAC_RX_STATS_IFERRORS_LOW 0x01CD
|
||||
|
||||
/*tx_stats_unicast_FramesOK*/
|
||||
#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_HI 0x014E
|
||||
#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_LOW 0x014F
|
||||
|
||||
/*rx_stats_unicast_FramesOK*/
|
||||
#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_HI 0x01CE
|
||||
#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_LOW 0x01CF
|
||||
|
||||
/*tx_stats_unicast_FramesErr*/
|
||||
#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_HI 0x0150
|
||||
#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_LOW 0x0151
|
||||
|
||||
/*rx_stats_unicast_FramesErr*/
|
||||
#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_HI 0x01D0
|
||||
#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_LOW 0x01D1
|
||||
|
||||
/*tx_stats_multicast_FramesOK*/
|
||||
#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_HI 0x0152
|
||||
#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_LOW 0x0153
|
||||
|
||||
/*rx_stats_multicast_FramesOK*/
|
||||
#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_HI 0x01D2
|
||||
#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_LOW 0x01D3
|
||||
|
||||
/*tx_stats_multicast_FramesErr*/
|
||||
#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_HI 0x0154
|
||||
#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_LOW 0x0155
|
||||
|
||||
/*rx_stats_multicast_FramesErr*/
|
||||
#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_HI 0x01D4
|
||||
#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_LOW 0x01D5
|
||||
|
||||
/*tx_stats_broadcast_FramesOK*/
|
||||
#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_HI 0x0156
|
||||
#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_LOW 0x0157
|
||||
|
||||
/*rx_stats_broadcast_FramesOK*/
|
||||
#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_HI 0x01D6
|
||||
#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_LOW 0x01D7
|
||||
|
||||
/*tx_stats_broadcast_FramesErr*/
|
||||
#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_HI 0x0158
|
||||
#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_LOW 0x0159
|
||||
|
||||
/*rx_stats_broadcast_FramesErr*/
|
||||
#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_HI 0x01D8
|
||||
#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_LOW 0x01D9
|
||||
|
||||
/*tx_stats_etherStatsOctets 64b*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_HI 0x015A
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_LOW 0x015B
|
||||
|
||||
/*rx_stats_etherStatsOctets 64b*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_HI 0x01DA
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_LOW 0x01DB
|
||||
|
||||
/*tx_stats_etherStatsPkts*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_HI 0x015C
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_LOW 0x015D
|
||||
|
||||
/*rx_stats_etherStatsPkts*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_HI 0x01DC
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_LOW 0x01DD
|
||||
|
||||
/*tx_stats_etherStatsUndersizePkts*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x015E
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x015F
|
||||
|
||||
/*rx_stats_etherStatsUndersizePkts*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x01DE
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x01DF
|
||||
|
||||
/*tx_stats_etherStatsOversizePkts*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x0160
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x0161
|
||||
|
||||
/*rx_stats_etherStatsOversizePkts*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x01E0
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x01E1
|
||||
|
||||
/*tx_stats_etherStatsPkts64Octets*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x0162
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x0163
|
||||
|
||||
/*rx_stats_etherStatsPkts64Octets*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x01E2
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x01E3
|
||||
|
||||
/*tx_stats_etherStatsPkts65to127Octets*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI 0x0164
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x0165
|
||||
|
||||
/*rx_stats_etherStatsPkts65to127Octets*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI 0x01E4
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x01E5
|
||||
|
||||
/*tx_stats_etherStatsPkts128to255Octets*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI 0x0166
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x0167
|
||||
|
||||
/*rx_stats_etherStatsPkts128to255Octets*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI 0x01E6
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x01E7
|
||||
|
||||
/*tx_stats_etherStatsPkts256to511Octet*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_HI 0x0168
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_LOW 0x0169
|
||||
|
||||
/*rx_stats_etherStatsPkts256to511Octets*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_HI 0x01E8
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_LOW 0x01E9
|
||||
|
||||
/*tx_stats_etherStatsPkts512to1023Octets*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI 0x016A
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x016B
|
||||
|
||||
/*rx_stats_etherStatsPkts512to1023Octets*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI 0x01EA
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x01EB
|
||||
|
||||
/*tx_stats_etherStatPkts1024to1518Octets*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI 0x016C
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x016D
|
||||
|
||||
/*rx_stats_etherStatPkts1024to1518Octets*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI 0x01EC
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x01ED
|
||||
|
||||
/*tx_stats_etherStatsPkts1519toXOctets*/
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI 0x016E
|
||||
#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x016F
|
||||
|
||||
/*rx_stats_etherStatsPkts1519toXOctets*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI 0x01EE
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x01EF
|
||||
|
||||
/*rx_stats_etherStatsFragments*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_HI 0x01F0
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_LOW 0x01F1
|
||||
|
||||
/*rx_stats_etherStatsJabbers*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_HI 0x01F2
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_LOW 0x01F3
|
||||
|
||||
/*rx_stats_etherStatsCRCErr*/
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_HI 0x01F4
|
||||
#define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_LOW 0x01F5
|
||||
|
||||
/*tx_stats_unicastMACCtrlFrames*/
|
||||
#define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_HI 0x0176
|
||||
#define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_LOW 0x0177
|
||||
|
||||
/*rx_stats_unicastMACCtrlFrames*/
|
||||
#define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_HI 0x01F6
|
||||
#define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_LOW 0x01F7
|
||||
|
||||
/*tx_stats_multicastMACCtrlFrames*/
|
||||
#define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_HI 0x0178
|
||||
#define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x0179
|
||||
|
||||
/*rx_stats_multicastMACCtrlFrames*/
|
||||
#define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_HI 0x01F8
|
||||
#define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x01F9
|
||||
|
||||
/*tx_stats_broadcastMACCtrlFrames*/
|
||||
#define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_HI 0x017A
|
||||
#define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x017B
|
||||
|
||||
/*rx_stats_broadcastMACCtrlFrames*/
|
||||
#define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_HI 0x01FA
|
||||
#define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x01FB
|
||||
|
||||
/*tx_stats_PFCMACCtrlFrames*/
|
||||
#define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_HI 0x017C
|
||||
#define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_LOW 0x017D
|
||||
|
||||
/*rx_stats_PFCMACCtrlFrames*/
|
||||
#define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_HI 0x01FC
|
||||
#define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_LOW 0x01FD
|
||||
#define IPN3KE_10G_TX_STATS_FRAME_OK_LO 0x0142
|
||||
#define IPN3KE_10G_TX_STATS_FRAME_OK_HI 0x0143
|
||||
#define IPN3KE_10G_RX_STATS_FRAME_OK_LO 0x01C2
|
||||
#define IPN3KE_10G_RX_STATS_FRAME_OK_HI 0x01C3
|
||||
#define IPN3KE_10G_TX_STATS_FRAME_ERR_LO 0x0144
|
||||
#define IPN3KE_10G_TX_STATS_FRAME_ERR_HI 0x0145
|
||||
#define IPN3KE_10G_RX_STATS_FRAME_ERR_LO 0x01C4
|
||||
#define IPN3KE_10G_RX_STATS_FRAME_ERR_HI 0x01C5
|
||||
#define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_LO 0x01C6
|
||||
#define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_HI 0x01C7
|
||||
#define IPN3KE_10G_TX_STATS_OCTETS_OK_LO 0x0148
|
||||
#define IPN3KE_10G_TX_STATS_OCTETS_OK_HI 0x0149
|
||||
#define IPN3KE_10G_RX_STATS_OCTETS_OK_LO 0x01C8
|
||||
#define IPN3KE_10G_RX_STATS_OCTETS_OK_HI 0x01C9
|
||||
#define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_LO 0x014A
|
||||
#define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_HI 0x014B
|
||||
#define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_LO 0x01CA
|
||||
#define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_HI 0x01CB
|
||||
#define IPN3KE_10G_TX_STATS_IF_ERRORS_LO 0x014C
|
||||
#define IPN3KE_10G_TX_STATS_IF_ERRORS_HI 0x014D
|
||||
#define IPN3KE_10G_RX_STATS_IF_ERRORS_LO 0x01CC
|
||||
#define IPN3KE_10G_RX_STATS_IF_ERRORS_HI 0x01CD
|
||||
#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_LO 0x014E
|
||||
#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_HI 0x014F
|
||||
#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_LO 0x01CE
|
||||
#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_HI 0x01CF
|
||||
#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_LO 0x0150
|
||||
#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_HI 0x0151
|
||||
#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_LO 0x01D0
|
||||
#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_HI 0x01D1
|
||||
#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_LO 0x0152
|
||||
#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_HI 0x0153
|
||||
#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_LO 0x01D2
|
||||
#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_HI 0x01D3
|
||||
#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_LO 0x0154
|
||||
#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_HI 0x0155
|
||||
#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_LO 0x01D4
|
||||
#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_HI 0x01D5
|
||||
#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_LO 0x0156
|
||||
#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_HI 0x0157
|
||||
#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_LO 0x01D6
|
||||
#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_HI 0x01D7
|
||||
#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_LO 0x0158
|
||||
#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_HI 0x0159
|
||||
#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_LO 0x01D8
|
||||
#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_HI 0x01D9
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_LO 0x015A
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_HI 0x015B
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_LO 0x01DA
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_HI 0x01DB
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_LO 0x015C
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_HI 0x015D
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_LO 0x01DC
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_HI 0x01DD
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO 0x015E
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI 0x015F
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO 0x01DE
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI 0x01DF
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO 0x0160
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI 0x0161
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO 0x01E0
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI 0x01E1
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO 0x0162
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI 0x0163
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO 0x01E2
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI 0x01E3
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO 0x0164
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI 0x0165
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO 0x01E4
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI 0x01E5
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO 0x0166
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI 0x0167
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO 0x01E6
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI 0x01E7
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO 0x0168
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI 0x0169
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO 0x01E8
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI 0x01E9
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO 0x016A
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI 0x016B
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO 0x01EA
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI 0x01EB
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO 0x016C
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI 0x016D
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO 0x01EC
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI 0x01ED
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO 0x016E
|
||||
#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI 0x016F
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO 0x01EE
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI 0x01EF
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_LO 0x01E0
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_HI 0x01F1
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_LO 0x01E2
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_HI 0x01F3
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_LO 0x01E4
|
||||
#define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_HI 0x01F5
|
||||
#define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_LO 0x0176
|
||||
#define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_HI 0x0177
|
||||
#define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_LO 0x01F6
|
||||
#define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_HI 0x01F7
|
||||
#define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO 0x0178
|
||||
#define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI 0x0179
|
||||
#define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO 0x01F8
|
||||
#define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI 0x01F9
|
||||
#define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO 0x017A
|
||||
#define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI 0x017B
|
||||
#define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO 0x01FA
|
||||
#define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI 0x01FB
|
||||
#define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_LO 0x017C
|
||||
#define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_HI 0x017D
|
||||
#define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_LO 0x01FC
|
||||
#define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_HI 0x01FD
|
||||
|
||||
static inline void ipn3ke_xmac_tx_enable(struct ipn3ke_hw *hw,
|
||||
uint32_t mac_num, uint32_t eth_group_sel)
|
||||
@ -949,31 +1008,72 @@ static inline void ipn3ke_xmac_smac_ovd_dis(struct ipn3ke_hw *hw,
|
||||
eth_group_sel);
|
||||
}
|
||||
|
||||
static inline void ipn3ke_xmac_tx_clr_stcs(struct ipn3ke_hw *hw,
|
||||
uint32_t mac_num, uint32_t eth_group_sel)
|
||||
static inline void ipn3ke_xmac_tx_clr_10G_stcs
|
||||
(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
|
||||
{
|
||||
#define IPN3KE_XMAC_TX_CLR_STCS (1 & \
|
||||
(IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK))
|
||||
|
||||
uint32_t tmp;
|
||||
tmp = 0x00000000;
|
||||
(*hw->f_mac_read)(hw,
|
||||
&tmp,
|
||||
IPN3KE_10G_TX_STATS_CLR,
|
||||
mac_num,
|
||||
eth_group_sel);
|
||||
tmp |= 0x00000001;
|
||||
(*hw->f_mac_write)(hw,
|
||||
IPN3KE_XMAC_TX_CLR_STCS,
|
||||
IPN3KE_MAC_TX_STATS_CLR,
|
||||
tmp,
|
||||
IPN3KE_10G_TX_STATS_CLR,
|
||||
mac_num,
|
||||
eth_group_sel);
|
||||
}
|
||||
|
||||
static inline void ipn3ke_xmac_rx_clr_stcs(struct ipn3ke_hw *hw,
|
||||
uint32_t mac_num, uint32_t eth_group_sel)
|
||||
static inline void ipn3ke_xmac_rx_clr_10G_stcs
|
||||
(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
|
||||
{
|
||||
#define IPN3KE_XMAC_RX_CLR_STCS (1 & \
|
||||
(IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK))
|
||||
|
||||
uint32_t tmp;
|
||||
tmp = 0x00000000;
|
||||
(*hw->f_mac_read)(hw,
|
||||
&tmp,
|
||||
IPN3KE_10G_RX_STATS_CLR,
|
||||
mac_num,
|
||||
eth_group_sel);
|
||||
tmp |= 0x00000001;
|
||||
(*hw->f_mac_write)(hw,
|
||||
IPN3KE_XMAC_RX_CLR_STCS,
|
||||
IPN3KE_MAC_RX_STATS_CLR,
|
||||
tmp,
|
||||
IPN3KE_10G_RX_STATS_CLR,
|
||||
mac_num,
|
||||
eth_group_sel);
|
||||
}
|
||||
|
||||
static inline void ipn3ke_xmac_tx_clr_25G_stcs
|
||||
(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
|
||||
{
|
||||
uint32_t tmp = 0x00000001;
|
||||
|
||||
/* Bit[0]: Software can set this bit to the value of 1
|
||||
* to reset all of the TX statistics registers at the same time.
|
||||
* This bit is selfclearing.
|
||||
*/
|
||||
(*hw->f_mac_write)(hw,
|
||||
tmp,
|
||||
IPN3KE_25G_TX_STATISTICS_CONFIG,
|
||||
mac_num,
|
||||
eth_group_sel);
|
||||
}
|
||||
|
||||
static inline void ipn3ke_xmac_rx_clr_25G_stcs
|
||||
(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)
|
||||
{
|
||||
uint32_t tmp = 0x00000001;
|
||||
|
||||
/* Bit[0]: Software can set this bit to the value of 1
|
||||
* to reset all of the RX statistics registers at the same time.
|
||||
* This bit is selfclearing.
|
||||
*/
|
||||
(*hw->f_mac_write)(hw,
|
||||
tmp,
|
||||
IPN3KE_25G_RX_STATISTICS_CONFIG,
|
||||
mac_num,
|
||||
eth_group_sel);
|
||||
}
|
||||
|
||||
#endif /* _IPN3KE_ETHDEV_H_ */
|
||||
|
||||
@ -159,11 +159,30 @@ ipn3ke_rpst_dev_start(struct rte_eth_dev *dev)
|
||||
/* Enable the RX path */
|
||||
ipn3ke_xmac_rx_enable(hw, rpst->port_id, 0);
|
||||
|
||||
/* Clear all TX statistics counters */
|
||||
ipn3ke_xmac_tx_clr_stcs(hw, rpst->port_id, 0);
|
||||
/* Clear line side TX statistics counters */
|
||||
ipn3ke_xmac_tx_clr_10G_stcs(hw, rpst->port_id, 0);
|
||||
|
||||
/* Clear all RX statistics counters */
|
||||
ipn3ke_xmac_rx_clr_stcs(hw, rpst->port_id, 0);
|
||||
/* Clear line side RX statistics counters */
|
||||
ipn3ke_xmac_rx_clr_10G_stcs(hw, rpst->port_id, 0);
|
||||
|
||||
/* Clear NIC side TX statistics counters */
|
||||
ipn3ke_xmac_tx_clr_10G_stcs(hw, rpst->port_id, 1);
|
||||
|
||||
/* Clear NIC side RX statistics counters */
|
||||
ipn3ke_xmac_rx_clr_10G_stcs(hw, rpst->port_id, 1);
|
||||
} else if (hw->retimer.mac_type ==
|
||||
IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {
|
||||
/* Clear line side TX statistics counters */
|
||||
ipn3ke_xmac_tx_clr_25G_stcs(hw, rpst->port_id, 0);
|
||||
|
||||
/* Clear line side RX statistics counters */
|
||||
ipn3ke_xmac_rx_clr_25G_stcs(hw, rpst->port_id, 0);
|
||||
|
||||
/* Clear NIC side TX statistics counters */
|
||||
ipn3ke_xmac_tx_clr_25G_stcs(hw, rpst->port_id, 1);
|
||||
|
||||
/* Clear NIC side RX statistics counters */
|
||||
ipn3ke_xmac_rx_clr_25G_stcs(hw, rpst->port_id, 1);
|
||||
}
|
||||
|
||||
ipn3ke_rpst_link_update(dev, 0);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user