baseband/fpga_5gnr_fec: add LDPC processing functions
Adding LDPC processing operations and related documentation. Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Dave Burley <dave.burley@accelercomm.com> Acked-by: Niall Power <niall.power@intel.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
This commit is contained in:
Nicolas Chautru
Akhil Goyal
parent
c58109a887
commit
44dc6faa79
@ -13,6 +13,8 @@ Features
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FPGA 5GNR FEC PMD supports the following features:
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- LDPC Encode in the DL
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- LDPC Decode in the UL
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- 8 VFs per PF (physical device)
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- Maximum of 32 UL queues per VF
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- Maximum of 32 DL queues per VF
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@ -20,6 +22,24 @@ FPGA 5GNR FEC PMD supports the following features:
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- MSI-X
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- SR-IOV
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FPGA 5GNR FEC PMD supports the following BBDEV capabilities:
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* For the LDPC encode operation:
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- ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
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- ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match bypass
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* For the LDPC decode operation:
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- ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s)
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- ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early termination
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- ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits appended while decoding
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- ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining
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- ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining
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- ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` : HARQ memory input is internal
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- ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` : HARQ memory output is internal
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- ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` : loopback data to/from HARQ memory
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- ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` : HARQ memory includes the fillers bits
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Limitations
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-----------
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@ -144,3 +164,11 @@ name is different:
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.. code-block:: console
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echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs
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Test Vectors
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~~~~~~~~~~~~
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In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
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a range of additional tests under the test_vectors folder, which may be useful. The results
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of these tests will depend on the FPGA 5GNR FEC capabilities.
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@ -53,6 +53,15 @@
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#define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8
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#define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8
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/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
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#define N_ZC_1 66 /* N = 66 Zc for BG 1 */
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#define N_ZC_2 50 /* N = 50 Zc for BG 2 */
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#define K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */
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#define K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */
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#define K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */
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#define K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */
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#define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */
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#define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */
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/* FPGA 5GNR FEC Register mapping on BAR0 */
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enum {
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@ -13,6 +13,9 @@
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#include <rte_pci.h>
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#include <rte_bus_pci.h>
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#include <rte_byteorder.h>
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#ifdef RTE_BBDEV_OFFLOAD_COST
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#include <rte_cycles.h>
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#endif
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#include <rte_bbdev.h>
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#include <rte_bbdev_pmd.h>
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@ -141,6 +144,40 @@ fpga_dev_info_get(struct rte_bbdev *dev,
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uint32_t q_id = 0;
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static const struct rte_bbdev_op_cap bbdev_capabilities[] = {
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{
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.type = RTE_BBDEV_OP_LDPC_ENC,
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.cap.ldpc_enc = {
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.capability_flags =
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RTE_BBDEV_LDPC_RATE_MATCH |
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RTE_BBDEV_LDPC_ENC_INTERRUPTS |
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RTE_BBDEV_LDPC_CRC_24B_ATTACH,
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.num_buffers_src =
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RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
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.num_buffers_dst =
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RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
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}
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},
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{
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.type = RTE_BBDEV_OP_LDPC_DEC,
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.cap.ldpc_dec = {
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.capability_flags =
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RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK |
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RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP |
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RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE |
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RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE |
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RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE |
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RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE |
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RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE |
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RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS,
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.llr_size = 6,
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.llr_decimals = 2,
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.num_buffers_src =
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RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
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.num_buffers_hard_out =
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RTE_BBDEV_LDPC_MAX_CODE_BLOCKS,
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.num_buffers_soft_out = 0,
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}
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},
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RTE_BBDEV_END_OF_CAPABILITIES_LIST()
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};
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@ -447,6 +484,625 @@ static const struct rte_bbdev_ops fpga_ops = {
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.queue_start = fpga_queue_start,
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.queue_release = fpga_queue_release,
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};
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static inline void
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fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc,
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struct rte_bbdev_stats *queue_stats)
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{
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#ifdef RTE_BBDEV_OFFLOAD_COST
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uint64_t start_time = 0;
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queue_stats->acc_offload_cycles = 0;
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#else
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RTE_SET_USED(queue_stats);
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#endif
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/* Update tail and shadow_tail register */
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q->tail = (q->tail + num_desc) & q->sw_ring_wrap_mask;
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rte_wmb();
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#ifdef RTE_BBDEV_OFFLOAD_COST
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/* Start time measurement for enqueue function offload. */
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start_time = rte_rdtsc_precise();
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#endif
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mmio_write_16(q->shadow_tail_addr, q->tail);
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#ifdef RTE_BBDEV_OFFLOAD_COST
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rte_wmb();
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queue_stats->acc_offload_cycles += rte_rdtsc_precise() - start_time;
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#endif
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}
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/* Read flag value 0/1/ from bitmap */
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static inline bool
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check_bit(uint32_t bitmap, uint32_t bitmask)
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{
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return bitmap & bitmask;
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}
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/* Compute value of k0.
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* Based on 3GPP 38.212 Table 5.4.2.1-2
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* Starting position of different redundancy versions, k0
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*/
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static inline uint16_t
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get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index)
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{
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if (rv_index == 0)
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return 0;
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uint16_t n = (bg == 1 ? N_ZC_1 : N_ZC_2) * z_c;
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if (n_cb == n) {
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if (rv_index == 1)
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return (bg == 1 ? K0_1_1 : K0_1_2) * z_c;
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else if (rv_index == 2)
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return (bg == 1 ? K0_2_1 : K0_2_2) * z_c;
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else
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return (bg == 1 ? K0_3_1 : K0_3_2) * z_c;
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}
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/* LBRM case - includes a division by N */
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if (rv_index == 1)
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return (((bg == 1 ? K0_1_1 : K0_1_2) * n_cb)
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/ n) * z_c;
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else if (rv_index == 2)
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return (((bg == 1 ? K0_2_1 : K0_2_2) * n_cb)
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/ n) * z_c;
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else
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return (((bg == 1 ? K0_3_1 : K0_3_2) * n_cb)
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/ n) * z_c;
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}
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/**
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* Set DMA descriptor for encode operation (1 Code Block)
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*
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* @param op
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* Pointer to a single encode operation.
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* @param desc
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* Pointer to DMA descriptor.
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* @param input
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* Pointer to pointer to input data which will be decoded.
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* @param e
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* E value (length of output in bits).
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* @param ncb
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* Ncb value (size of the soft buffer).
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* @param out_length
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* Length of output buffer
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* @param in_offset
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* Input offset in rte_mbuf structure. It is used for calculating the point
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* where data is starting.
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* @param out_offset
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* Output offset in rte_mbuf structure. It is used for calculating the point
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* where hard output data will be stored.
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* @param cbs_in_op
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* Number of CBs contained in one operation.
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*/
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static inline int
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fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op,
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struct fpga_dma_enc_desc *desc, struct rte_mbuf *input,
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struct rte_mbuf *output, uint16_t k_, uint16_t e,
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uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset,
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uint8_t cbs_in_op)
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{
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/* reset */
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desc->done = 0;
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desc->error = 0;
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desc->k_ = k_;
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desc->rm_e = e;
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desc->desc_idx = desc_offset;
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desc->zc = op->ldpc_enc.z_c;
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desc->bg_idx = op->ldpc_enc.basegraph - 1;
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desc->qm_idx = op->ldpc_enc.q_m / 2;
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desc->crc_en = check_bit(op->ldpc_enc.op_flags,
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RTE_BBDEV_LDPC_CRC_24B_ATTACH);
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desc->irq_en = 0;
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desc->k0 = get_k0(op->ldpc_enc.n_cb, op->ldpc_enc.z_c,
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op->ldpc_enc.basegraph, op->ldpc_enc.rv_index);
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desc->ncb = op->ldpc_enc.n_cb;
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desc->num_null = op->ldpc_enc.n_filler;
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/* Set inbound data buffer address */
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desc->in_addr_hi = (uint32_t)(
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rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
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desc->in_addr_lw = (uint32_t)(
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rte_pktmbuf_mtophys_offset(input, in_offset));
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desc->out_addr_hi = (uint32_t)(
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rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
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desc->out_addr_lw = (uint32_t)(
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rte_pktmbuf_mtophys_offset(output, out_offset));
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/* Save software context needed for dequeue */
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desc->op_addr = op;
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/* Set total number of CBs in an op */
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desc->cbs_in_op = cbs_in_op;
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return 0;
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}
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/**
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* Set DMA descriptor for decode operation (1 Code Block)
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*
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* @param op
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* Pointer to a single encode operation.
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* @param desc
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* Pointer to DMA descriptor.
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* @param input
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* Pointer to pointer to input data which will be decoded.
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* @param in_offset
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* Input offset in rte_mbuf structure. It is used for calculating the point
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* where data is starting.
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* @param out_offset
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* Output offset in rte_mbuf structure. It is used for calculating the point
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* where hard output data will be stored.
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* @param cbs_in_op
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* Number of CBs contained in one operation.
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*/
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static inline int
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fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,
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struct fpga_dma_dec_desc *desc,
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struct rte_mbuf *input, struct rte_mbuf *output,
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uint16_t harq_in_length,
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uint32_t in_offset, uint32_t out_offset,
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uint32_t harq_offset,
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uint16_t desc_offset,
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uint8_t cbs_in_op)
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{
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/* reset */
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desc->done = 0;
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desc->error = 0;
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/* Set inbound data buffer address */
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desc->in_addr_hi = (uint32_t)(
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rte_pktmbuf_mtophys_offset(input, in_offset) >> 32);
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desc->in_addr_lw = (uint32_t)(
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rte_pktmbuf_mtophys_offset(input, in_offset));
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desc->rm_e = op->ldpc_dec.cb_params.e;
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desc->harq_input_length = harq_in_length;
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desc->et_dis = !check_bit(op->ldpc_dec.op_flags,
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RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);
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desc->rv = op->ldpc_dec.rv_index;
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desc->crc24b_ind = check_bit(op->ldpc_dec.op_flags,
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RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);
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desc->drop_crc24b = check_bit(op->ldpc_dec.op_flags,
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RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP);
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desc->desc_idx = desc_offset;
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desc->ncb = op->ldpc_dec.n_cb;
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desc->num_null = op->ldpc_dec.n_filler;
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desc->hbstroe_offset = harq_offset >> 10;
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desc->zc = op->ldpc_dec.z_c;
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desc->harqin_en = check_bit(op->ldpc_dec.op_flags,
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RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);
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desc->bg_idx = op->ldpc_dec.basegraph - 1;
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desc->max_iter = op->ldpc_dec.iter_max;
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desc->qm_idx = op->ldpc_dec.q_m / 2;
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desc->out_addr_hi = (uint32_t)(
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rte_pktmbuf_mtophys_offset(output, out_offset) >> 32);
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desc->out_addr_lw = (uint32_t)(
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rte_pktmbuf_mtophys_offset(output, out_offset));
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/* Save software context needed for dequeue */
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desc->op_addr = op;
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/* Set total number of CBs in an op */
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desc->cbs_in_op = cbs_in_op;
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return 0;
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}
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static inline char *
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mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)
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{
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if (unlikely(len > rte_pktmbuf_tailroom(m)))
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return NULL;
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char *tail = (char *)m->buf_addr + m->data_off + m->data_len;
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m->data_len = (uint16_t)(m->data_len + len);
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m_head->pkt_len = (m_head->pkt_len + len);
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return tail;
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}
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static inline int
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enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
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uint16_t desc_offset)
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{
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union fpga_dma_desc *desc;
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int ret;
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uint8_t c, crc24_bits = 0;
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struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc;
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uint16_t in_offset = enc->input.offset;
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uint16_t out_offset = enc->output.offset;
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struct rte_mbuf *m_in = enc->input.data;
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struct rte_mbuf *m_out = enc->output.data;
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struct rte_mbuf *m_out_head = enc->output.data;
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uint32_t in_length, out_length, e;
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uint16_t total_left = enc->input.length;
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uint16_t ring_offset;
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uint16_t K, k_;
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/* Clear op status */
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op->status = 0;
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if (m_in == NULL || m_out == NULL) {
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rte_bbdev_log(ERR, "Invalid mbuf pointer");
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op->status = 1 << RTE_BBDEV_DATA_ERROR;
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return -EINVAL;
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}
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if (enc->op_flags & RTE_BBDEV_LDPC_CRC_24B_ATTACH)
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crc24_bits = 24;
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if (enc->code_block_mode == 0) {
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/* For Transport Block mode */
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/* FIXME */
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c = enc->tb_params.c;
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e = enc->tb_params.ea;
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} else { /* For Code Block mode */
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c = 1;
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e = enc->cb_params.e;
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}
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/* Update total_left */
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K = (enc->basegraph == 1 ? 22 : 10) * enc->z_c;
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k_ = K - enc->n_filler;
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in_length = (k_ - crc24_bits) >> 3;
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out_length = (e + 7) >> 3;
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total_left = rte_pktmbuf_data_len(m_in) - in_offset;
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/* Update offsets */
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if (total_left != in_length) {
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op->status |= 1 << RTE_BBDEV_DATA_ERROR;
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rte_bbdev_log(ERR,
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"Mismatch between mbuf length and included CBs sizes %d",
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total_left);
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}
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mbuf_append(m_out_head, m_out, out_length);
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/* Offset into the ring */
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ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
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/* Setup DMA Descriptor */
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desc = q->ring_addr + ring_offset;
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ret = fpga_dma_desc_te_fill(op, &desc->enc_req, m_in, m_out,
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k_, e, in_offset, out_offset, ring_offset, c);
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if (unlikely(ret < 0))
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return ret;
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/* Update lengths */
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total_left -= in_length;
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op->ldpc_enc.output.length += out_length;
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if (total_left > 0) {
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rte_bbdev_log(ERR,
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"Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
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total_left, in_length);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline int
|
||||
enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
|
||||
uint16_t desc_offset)
|
||||
{
|
||||
union fpga_dma_desc *desc;
|
||||
int ret;
|
||||
uint16_t ring_offset;
|
||||
uint8_t c;
|
||||
uint16_t e, in_length, out_length, k0, l, seg_total_left, sys_cols;
|
||||
uint16_t K, parity_offset, harq_in_length = 0, harq_out_length = 0;
|
||||
uint16_t crc24_overlap = 0;
|
||||
struct rte_bbdev_op_ldpc_dec *dec = &op->ldpc_dec;
|
||||
struct rte_mbuf *m_in = dec->input.data;
|
||||
struct rte_mbuf *m_out = dec->hard_output.data;
|
||||
struct rte_mbuf *m_out_head = dec->hard_output.data;
|
||||
uint16_t in_offset = dec->input.offset;
|
||||
uint16_t out_offset = dec->hard_output.offset;
|
||||
uint32_t harq_offset = 0;
|
||||
|
||||
/* Clear op status */
|
||||
op->status = 0;
|
||||
|
||||
/* Setup DMA Descriptor */
|
||||
ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask);
|
||||
desc = q->ring_addr + ring_offset;
|
||||
|
||||
if (m_in == NULL || m_out == NULL) {
|
||||
rte_bbdev_log(ERR, "Invalid mbuf pointer");
|
||||
op->status = 1 << RTE_BBDEV_DATA_ERROR;
|
||||
return -1;
|
||||
}
|
||||
|
||||
c = 1;
|
||||
e = dec->cb_params.e;
|
||||
|
||||
if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP))
|
||||
crc24_overlap = 24;
|
||||
|
||||
sys_cols = (dec->basegraph == 1) ? 22 : 10;
|
||||
K = sys_cols * dec->z_c;
|
||||
parity_offset = K - 2 * dec->z_c;
|
||||
|
||||
out_length = ((K - crc24_overlap - dec->n_filler) >> 3);
|
||||
in_length = e;
|
||||
seg_total_left = dec->input.length;
|
||||
|
||||
if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) {
|
||||
harq_in_length = RTE_MIN(dec->harq_combined_input.length,
|
||||
(uint32_t)dec->n_cb);
|
||||
}
|
||||
|
||||
if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) {
|
||||
k0 = get_k0(dec->n_cb, dec->z_c,
|
||||
dec->basegraph, dec->rv_index);
|
||||
if (k0 > parity_offset)
|
||||
l = k0 + e;
|
||||
else
|
||||
l = k0 + e + dec->n_filler;
|
||||
harq_out_length = RTE_MIN(RTE_MAX(harq_in_length, l),
|
||||
dec->n_cb - dec->n_filler);
|
||||
dec->harq_combined_output.length = harq_out_length;
|
||||
}
|
||||
|
||||
mbuf_append(m_out_head, m_out, out_length);
|
||||
if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE))
|
||||
harq_offset = dec->harq_combined_input.offset;
|
||||
else if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE))
|
||||
harq_offset = dec->harq_combined_output.offset;
|
||||
|
||||
if ((harq_offset & 0x3FF) > 0) {
|
||||
rte_bbdev_log(ERR, "Invalid HARQ offset %d", harq_offset);
|
||||
op->status = 1 << RTE_BBDEV_DATA_ERROR;
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret = fpga_dma_desc_ld_fill(op, &desc->dec_req, m_in, m_out,
|
||||
harq_in_length, in_offset, out_offset, harq_offset,
|
||||
ring_offset, c);
|
||||
if (unlikely(ret < 0))
|
||||
return ret;
|
||||
/* Update lengths */
|
||||
seg_total_left -= in_length;
|
||||
op->ldpc_dec.hard_output.length += out_length;
|
||||
if (seg_total_left > 0) {
|
||||
rte_bbdev_log(ERR,
|
||||
"Mismatch between mbuf length and included CB sizes: mbuf len %u, cb len %u",
|
||||
seg_total_left, in_length);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
fpga_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_enc_op **ops, uint16_t num)
|
||||
{
|
||||
uint16_t i, total_enqueued_cbs = 0;
|
||||
int32_t avail;
|
||||
int enqueued_cbs;
|
||||
struct fpga_queue *q = q_data->queue_private;
|
||||
union fpga_dma_desc *desc;
|
||||
|
||||
/* Check if queue is not full */
|
||||
if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
|
||||
q->head_free_desc))
|
||||
return 0;
|
||||
|
||||
/* Calculates available space */
|
||||
avail = (q->head_free_desc > q->tail) ?
|
||||
q->head_free_desc - q->tail - 1 :
|
||||
q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
|
||||
|
||||
for (i = 0; i < num; ++i) {
|
||||
|
||||
/* Check if there is available space for further
|
||||
* processing
|
||||
*/
|
||||
if (unlikely(avail - 1 < 0))
|
||||
break;
|
||||
avail -= 1;
|
||||
enqueued_cbs = enqueue_ldpc_enc_one_op_cb(q, ops[i],
|
||||
total_enqueued_cbs);
|
||||
|
||||
if (enqueued_cbs < 0)
|
||||
break;
|
||||
|
||||
total_enqueued_cbs += enqueued_cbs;
|
||||
|
||||
rte_bbdev_log_debug("enqueuing enc ops [%d/%d] | head %d | tail %d",
|
||||
total_enqueued_cbs, num,
|
||||
q->head_free_desc, q->tail);
|
||||
}
|
||||
|
||||
/* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
|
||||
* only when all previous CBs were already processed.
|
||||
*/
|
||||
desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
|
||||
& q->sw_ring_wrap_mask);
|
||||
desc->enc_req.irq_en = q->irq_enable;
|
||||
|
||||
fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
|
||||
|
||||
/* Update stats */
|
||||
q_data->queue_stats.enqueued_count += i;
|
||||
q_data->queue_stats.enqueue_err_count += num - i;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
fpga_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_dec_op **ops, uint16_t num)
|
||||
{
|
||||
uint16_t i, total_enqueued_cbs = 0;
|
||||
int32_t avail;
|
||||
int enqueued_cbs;
|
||||
struct fpga_queue *q = q_data->queue_private;
|
||||
union fpga_dma_desc *desc;
|
||||
|
||||
/* Check if queue is not full */
|
||||
if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) ==
|
||||
q->head_free_desc))
|
||||
return 0;
|
||||
|
||||
/* Calculates available space */
|
||||
avail = (q->head_free_desc > q->tail) ?
|
||||
q->head_free_desc - q->tail - 1 :
|
||||
q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1;
|
||||
|
||||
for (i = 0; i < num; ++i) {
|
||||
|
||||
/* Check if there is available space for further
|
||||
* processing
|
||||
*/
|
||||
if (unlikely(avail - 1 < 0))
|
||||
break;
|
||||
avail -= 1;
|
||||
enqueued_cbs = enqueue_ldpc_dec_one_op_cb(q, ops[i],
|
||||
total_enqueued_cbs);
|
||||
|
||||
if (enqueued_cbs < 0)
|
||||
break;
|
||||
|
||||
total_enqueued_cbs += enqueued_cbs;
|
||||
|
||||
rte_bbdev_log_debug("enqueuing dec ops [%d/%d] | head %d | tail %d",
|
||||
total_enqueued_cbs, num,
|
||||
q->head_free_desc, q->tail);
|
||||
}
|
||||
|
||||
/* Update stats */
|
||||
q_data->queue_stats.enqueued_count += i;
|
||||
q_data->queue_stats.enqueue_err_count += num - i;
|
||||
|
||||
/* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt
|
||||
* only when all previous CBs were already processed.
|
||||
*/
|
||||
desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1)
|
||||
& q->sw_ring_wrap_mask);
|
||||
desc->enc_req.irq_en = q->irq_enable;
|
||||
fpga_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats);
|
||||
return i;
|
||||
}
|
||||
|
||||
|
||||
static inline int
|
||||
dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q,
|
||||
struct rte_bbdev_enc_op **op __rte_unused,
|
||||
uint16_t desc_offset)
|
||||
{
|
||||
union fpga_dma_desc *desc;
|
||||
|
||||
/* Set current desc */
|
||||
desc = q->ring_addr + ((q->head_free_desc + desc_offset)
|
||||
& q->sw_ring_wrap_mask);
|
||||
|
||||
/*check if done */
|
||||
if (desc->enc_req.done == 0)
|
||||
return -1;
|
||||
|
||||
/* make sure the response is read atomically */
|
||||
rte_smp_rmb();
|
||||
|
||||
rte_bbdev_log_debug("DMA response desc %p", desc);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
static inline int
|
||||
dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,
|
||||
uint16_t desc_offset)
|
||||
{
|
||||
union fpga_dma_desc *desc;
|
||||
|
||||
/* Set descriptor */
|
||||
desc = q->ring_addr + ((q->head_free_desc + desc_offset)
|
||||
& q->sw_ring_wrap_mask);
|
||||
|
||||
/* Verify done bit is set */
|
||||
if (desc->dec_req.done == 0)
|
||||
return -1;
|
||||
|
||||
/* make sure the response is read atomically */
|
||||
rte_smp_rmb();
|
||||
|
||||
*op = desc->dec_req.op_addr;
|
||||
|
||||
if (check_bit((*op)->ldpc_dec.op_flags,
|
||||
RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) {
|
||||
(*op)->status = 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* FPGA reports iterations based on round-up minus 1 */
|
||||
(*op)->ldpc_dec.iter_count = desc->dec_req.iter + 1;
|
||||
/* CRC Check criteria */
|
||||
if (desc->dec_req.crc24b_ind && !(desc->dec_req.crcb_pass))
|
||||
(*op)->status = 1 << RTE_BBDEV_CRC_ERROR;
|
||||
/* et_pass = 0 when decoder fails */
|
||||
(*op)->status |= !(desc->dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR;
|
||||
return 1;
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
fpga_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_enc_op **ops, uint16_t num)
|
||||
{
|
||||
struct fpga_queue *q = q_data->queue_private;
|
||||
uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
|
||||
uint16_t i;
|
||||
uint16_t dequeued_cbs = 0;
|
||||
int ret;
|
||||
|
||||
for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
|
||||
ret = dequeue_ldpc_enc_one_op_cb(q, &ops[i], dequeued_cbs);
|
||||
|
||||
if (ret < 0)
|
||||
break;
|
||||
|
||||
dequeued_cbs += ret;
|
||||
|
||||
rte_bbdev_log_debug("dequeuing enc ops [%d/%d] | head %d | tail %d",
|
||||
dequeued_cbs, num, q->head_free_desc, q->tail);
|
||||
}
|
||||
|
||||
/* Update head */
|
||||
q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
|
||||
q->sw_ring_wrap_mask;
|
||||
|
||||
/* Update stats */
|
||||
q_data->queue_stats.dequeued_count += i;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
fpga_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data,
|
||||
struct rte_bbdev_dec_op **ops, uint16_t num)
|
||||
{
|
||||
struct fpga_queue *q = q_data->queue_private;
|
||||
uint32_t avail = (q->tail - q->head_free_desc) & q->sw_ring_wrap_mask;
|
||||
uint16_t i;
|
||||
uint16_t dequeued_cbs = 0;
|
||||
int ret;
|
||||
|
||||
for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) {
|
||||
ret = dequeue_ldpc_dec_one_op_cb(q, &ops[i], dequeued_cbs);
|
||||
|
||||
if (ret < 0)
|
||||
break;
|
||||
|
||||
dequeued_cbs += ret;
|
||||
|
||||
rte_bbdev_log_debug("dequeuing dec ops [%d/%d] | head %d | tail %d",
|
||||
dequeued_cbs, num, q->head_free_desc, q->tail);
|
||||
}
|
||||
|
||||
/* Update head */
|
||||
q->head_free_desc = (q->head_free_desc + dequeued_cbs) &
|
||||
q->sw_ring_wrap_mask;
|
||||
|
||||
/* Update stats */
|
||||
q_data->queue_stats.dequeued_count += i;
|
||||
|
||||
return i;
|
||||
}
|
||||
|
||||
|
||||
/* Initialization Function */
|
||||
static void
|
||||
@ -455,6 +1111,10 @@ fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)
|
||||
struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
|
||||
|
||||
dev->dev_ops = &fpga_ops;
|
||||
dev->enqueue_ldpc_enc_ops = fpga_enqueue_ldpc_enc;
|
||||
dev->enqueue_ldpc_dec_ops = fpga_enqueue_ldpc_dec;
|
||||
dev->dequeue_ldpc_enc_ops = fpga_dequeue_ldpc_enc;
|
||||
dev->dequeue_ldpc_dec_ops = fpga_dequeue_ldpc_dec;
|
||||
|
||||
((struct fpga_5gnr_fec_device *) dev->data->dev_private)->pf_device =
|
||||
!strcmp(drv->driver.name,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user