net/i40e: implement descriptor status API
Signed-off-by: Olivier Matz <olivier.matz@6wind.com> Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
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@ -38,6 +38,8 @@ Inner L3 checksum = Y
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Inner L4 checksum = Y
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Packet type parsing = Y
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Timesync = Y
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Rx descriptor status = Y
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Tx descriptor status = Y
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Basic stats = Y
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Extended stats = Y
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FW version = Y
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@ -29,6 +29,8 @@ Flow director = Y
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Flow control = Y
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Traffic mirroring = Y
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Timesync = Y
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Rx descriptor status = Y
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Tx descriptor status = Y
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Basic stats = Y
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Extended stats = Y
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Multiprocess aware = Y
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@ -26,6 +26,8 @@ L4 checksum offload = Y
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Inner L3 checksum = Y
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Inner L4 checksum = Y
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Packet type parsing = Y
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Rx descriptor status = Y
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Tx descriptor status = Y
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Basic stats = Y
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Extended stats = Y
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Multiprocess aware = Y
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@ -18,6 +18,8 @@ RSS key update = Y
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RSS reta update = Y
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VLAN filter = Y
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Hash filter = Y
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Rx descriptor status = Y
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Tx descriptor status = Y
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Basic stats = Y
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Extended stats = Y
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Multiprocess aware = Y
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@ -479,6 +479,8 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {
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.rx_queue_release = i40e_dev_rx_queue_release,
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.rx_queue_count = i40e_dev_rx_queue_count,
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.rx_descriptor_done = i40e_dev_rx_descriptor_done,
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.rx_descriptor_status = i40e_dev_rx_descriptor_status,
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.tx_descriptor_status = i40e_dev_tx_descriptor_status,
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.tx_queue_setup = i40e_dev_tx_queue_setup,
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.tx_queue_release = i40e_dev_tx_queue_release,
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.dev_led_on = i40e_dev_led_on,
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@ -217,6 +217,8 @@ static const struct eth_dev_ops i40evf_eth_dev_ops = {
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.rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
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.rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
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.rx_descriptor_done = i40e_dev_rx_descriptor_done,
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.rx_descriptor_status = i40e_dev_rx_descriptor_status,
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.tx_descriptor_status = i40e_dev_tx_descriptor_status,
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.tx_queue_setup = i40e_dev_tx_queue_setup,
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.tx_queue_release = i40e_dev_tx_queue_release,
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.rx_queue_count = i40e_dev_rx_queue_count,
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@ -1923,6 +1923,64 @@ i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
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return ret;
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}
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int
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i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
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{
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struct i40e_rx_queue *rxq = rx_queue;
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volatile uint64_t *status;
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uint64_t mask;
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uint32_t desc;
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if (unlikely(offset >= rxq->nb_rx_desc))
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return -EINVAL;
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if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
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return RTE_ETH_RX_DESC_UNAVAIL;
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desc = rxq->rx_tail + offset;
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if (desc >= rxq->nb_rx_desc)
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desc -= rxq->nb_rx_desc;
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status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
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mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
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<< I40E_RXD_QW1_STATUS_SHIFT);
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if (*status & mask)
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return RTE_ETH_RX_DESC_DONE;
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return RTE_ETH_RX_DESC_AVAIL;
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}
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int
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i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
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{
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struct i40e_tx_queue *txq = tx_queue;
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volatile uint64_t *status;
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uint64_t mask, expect;
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uint32_t desc;
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if (unlikely(offset >= txq->nb_tx_desc))
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return -EINVAL;
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desc = txq->tx_tail + offset;
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/* go to next desc that has the RS bit */
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desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
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txq->tx_rs_thresh;
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if (desc >= txq->nb_tx_desc) {
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desc -= txq->nb_tx_desc;
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if (desc >= txq->nb_tx_desc)
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desc -= txq->nb_tx_desc;
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}
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status = &txq->tx_ring[desc].cmd_type_offset_bsz;
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mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
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expect = rte_cpu_to_le_64(
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I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
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if ((*status & mask) == expect)
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return RTE_ETH_TX_DESC_DONE;
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return RTE_ETH_TX_DESC_FULL;
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}
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int
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i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
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uint16_t queue_idx,
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@ -246,6 +246,8 @@ void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
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uint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev,
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uint16_t rx_queue_id);
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int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
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int i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
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int i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
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uint16_t i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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