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net/i40e: implement descriptor status API

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Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
This commit is contained in:
Olivier Matz 2017-03-29 10:36:33 +02:00 committed by Thomas Monjalon
parent a2919e13d9
commit 68a43d1bb0
8 changed files with 72 additions and 0 deletions
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2
doc/guides/nics/features/i40e.ini
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@ -38,6 +38,8 @@ Inner L3 checksum = Y
Inner L4 checksum = Y Inner L4 checksum = Y
Packet type parsing = Y Packet type parsing = Y
Timesync = Y Timesync = Y
Rx descriptor status = Y
Tx descriptor status = Y
Basic stats = Y Basic stats = Y
Extended stats = Y Extended stats = Y
FW version = Y FW version = Y

2
doc/guides/nics/features/i40e_vec.ini
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@ -29,6 +29,8 @@ Flow director = Y
Flow control = Y Flow control = Y
Traffic mirroring = Y Traffic mirroring = Y
Timesync = Y Timesync = Y
Rx descriptor status = Y
Tx descriptor status = Y
Basic stats = Y Basic stats = Y
Extended stats = Y Extended stats = Y
Multiprocess aware = Y Multiprocess aware = Y

2
doc/guides/nics/features/i40e_vf.ini
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@ -26,6 +26,8 @@ L4 checksum offload = Y
Inner L3 checksum = Y Inner L3 checksum = Y
Inner L4 checksum = Y Inner L4 checksum = Y
Packet type parsing = Y Packet type parsing = Y
Rx descriptor status = Y
Tx descriptor status = Y
Basic stats = Y Basic stats = Y
Extended stats = Y Extended stats = Y
Multiprocess aware = Y Multiprocess aware = Y

2
doc/guides/nics/features/i40e_vf_vec.ini
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@ -18,6 +18,8 @@ RSS key update = Y
RSS reta update = Y RSS reta update = Y
VLAN filter = Y VLAN filter = Y
Hash filter = Y Hash filter = Y
Rx descriptor status = Y
Tx descriptor status = Y
Basic stats = Y Basic stats = Y
Extended stats = Y Extended stats = Y
Multiprocess aware = Y Multiprocess aware = Y

2
drivers/net/i40e/i40e_ethdev.c
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@ -479,6 +479,8 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {
.rx_queue_release = i40e_dev_rx_queue_release, .rx_queue_release = i40e_dev_rx_queue_release,
.rx_queue_count = i40e_dev_rx_queue_count, .rx_queue_count = i40e_dev_rx_queue_count,
.rx_descriptor_done = i40e_dev_rx_descriptor_done, .rx_descriptor_done = i40e_dev_rx_descriptor_done,
.rx_descriptor_status = i40e_dev_rx_descriptor_status,
.tx_descriptor_status = i40e_dev_tx_descriptor_status,
.tx_queue_setup = i40e_dev_tx_queue_setup, .tx_queue_setup = i40e_dev_tx_queue_setup,
.tx_queue_release = i40e_dev_tx_queue_release, .tx_queue_release = i40e_dev_tx_queue_release,
.dev_led_on = i40e_dev_led_on, .dev_led_on = i40e_dev_led_on,

2
drivers/net/i40e/i40e_ethdev_vf.c
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@ -217,6 +217,8 @@ static const struct eth_dev_ops i40evf_eth_dev_ops = {
.rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable, .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
.rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable, .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
.rx_descriptor_done = i40e_dev_rx_descriptor_done, .rx_descriptor_done = i40e_dev_rx_descriptor_done,
.rx_descriptor_status = i40e_dev_rx_descriptor_status,
.tx_descriptor_status = i40e_dev_tx_descriptor_status,
.tx_queue_setup = i40e_dev_tx_queue_setup, .tx_queue_setup = i40e_dev_tx_queue_setup,
.tx_queue_release = i40e_dev_tx_queue_release, .tx_queue_release = i40e_dev_tx_queue_release,
.rx_queue_count = i40e_dev_rx_queue_count, .rx_queue_count = i40e_dev_rx_queue_count,

58
drivers/net/i40e/i40e_rxtx.c
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@ -1923,6 +1923,64 @@ i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
return ret; return ret;
} }
int
i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
{
struct i40e_rx_queue *rxq = rx_queue;
volatile uint64_t *status;
uint64_t mask;
uint32_t desc;
if (unlikely(offset >= rxq->nb_rx_desc))
return -EINVAL;
if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
return RTE_ETH_RX_DESC_UNAVAIL;
desc = rxq->rx_tail + offset;
if (desc >= rxq->nb_rx_desc)
desc -= rxq->nb_rx_desc;
status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
<< I40E_RXD_QW1_STATUS_SHIFT);
if (*status & mask)
return RTE_ETH_RX_DESC_DONE;
return RTE_ETH_RX_DESC_AVAIL;
}
int
i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
{
struct i40e_tx_queue *txq = tx_queue;
volatile uint64_t *status;
uint64_t mask, expect;
uint32_t desc;
if (unlikely(offset >= txq->nb_tx_desc))
return -EINVAL;
desc = txq->tx_tail + offset;
/* go to next desc that has the RS bit */
desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
txq->tx_rs_thresh;
if (desc >= txq->nb_tx_desc) {
desc -= txq->nb_tx_desc;
if (desc >= txq->nb_tx_desc)
desc -= txq->nb_tx_desc;
}
status = &txq->tx_ring[desc].cmd_type_offset_bsz;
mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
expect = rte_cpu_to_le_64(
I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
if ((*status & mask) == expect)
return RTE_ETH_TX_DESC_DONE;
return RTE_ETH_TX_DESC_FULL;
}
int int
i40e_dev_tx_queue_setup(struct rte_eth_dev *dev, i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
uint16_t queue_idx, uint16_t queue_idx,

2
drivers/net/i40e/i40e_rxtx.h
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@ -246,6 +246,8 @@ void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
uint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev,
uint16_t rx_queue_id); uint16_t rx_queue_id);
int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset); int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
int i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
int i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
uint16_t i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts); uint16_t nb_pkts);