raw/ifpga: add HE-MEM AFU driver
HE-MEM is one of the host exerciser modules in OFS FPGA, which is used to test local memory with built-in traffic generator. This driver initialize the module and report test result. Signed-off-by: Wei Huang <wei.huang@intel.com> Acked-by: Tianfei Zhang <tianfei.zhang@intel.com> Reviewed-by: Rosen Xu <rosen.xu@intel.com>
This commit is contained in:
Wei Huang
Thomas Monjalon
parent
a84edb506f
commit
72dbdec4da
183
drivers/raw/ifpga/afu_pmd_he_mem.c
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183
drivers/raw/ifpga/afu_pmd_he_mem.c
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@ -0,0 +1,183 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 Intel Corporation
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*/
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#include <errno.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <poll.h>
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#include <sys/eventfd.h>
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#include <sys/ioctl.h>
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#include <rte_eal.h>
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#include <rte_malloc.h>
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#include <rte_memcpy.h>
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#include <rte_io.h>
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#include <rte_vfio.h>
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#include <rte_bus_pci.h>
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#include <rte_bus_ifpga.h>
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#include <rte_rawdev.h>
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#include "afu_pmd_core.h"
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#include "afu_pmd_he_mem.h"
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static int he_mem_tg_test(struct afu_rawdev *dev)
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{
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struct he_mem_tg_priv *priv = NULL;
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struct rte_pmd_afu_he_mem_tg_cfg *cfg = NULL;
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struct he_mem_tg_ctx *ctx = NULL;
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uint64_t value = 0x12345678;
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uint64_t cap = 0;
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uint64_t channel_mask = 0;
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int i, t = 0;
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if (!dev)
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return -EINVAL;
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priv = (struct he_mem_tg_priv *)dev->priv;
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if (!priv)
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return -ENOENT;
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cfg = &priv->he_mem_tg_cfg;
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ctx = &priv->he_mem_tg_ctx;
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IFPGA_RAWDEV_PMD_DEBUG("Channel mask: 0x%x", cfg->channel_mask);
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rte_write64(value, ctx->addr + MEM_TG_SCRATCHPAD);
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cap = rte_read64(ctx->addr + MEM_TG_SCRATCHPAD);
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IFPGA_RAWDEV_PMD_DEBUG("Scratchpad value: 0x%"PRIx64, cap);
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if (cap != value) {
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IFPGA_RAWDEV_PMD_ERR("Test scratchpad register failed");
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return -EIO;
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}
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cap = rte_read64(ctx->addr + MEM_TG_CTRL);
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IFPGA_RAWDEV_PMD_DEBUG("Capability: 0x%"PRIx64, cap);
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channel_mask = cfg->channel_mask & cap;
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/* start traffic generators */
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rte_write64(channel_mask, ctx->addr + MEM_TG_CTRL);
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/* check test status */
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while (t < MEM_TG_TIMEOUT_MS) {
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value = rte_read64(ctx->addr + MEM_TG_STAT);
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for (i = 0; i < NUM_MEM_TG_CHANNELS; i++) {
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if (channel_mask & (1 << i)) {
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if (TGACTIVE(value, i))
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continue;
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printf("TG channel %d test %s\n", i,
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TGPASS(value, i) ? "pass" :
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TGTIMEOUT(value, i) ? "timeout" :
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TGFAIL(value, i) ? "fail" : "error");
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channel_mask &= ~(1 << i);
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}
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}
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if (!channel_mask)
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break;
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rte_delay_ms(MEM_TG_POLL_INTERVAL_MS);
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t += MEM_TG_POLL_INTERVAL_MS;
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}
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if (channel_mask) {
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IFPGA_RAWDEV_PMD_ERR("Timeout 0x%04lx", (unsigned long)value);
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return channel_mask;
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}
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return 0;
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}
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static int he_mem_tg_init(struct afu_rawdev *dev)
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{
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struct he_mem_tg_priv *priv = NULL;
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struct he_mem_tg_ctx *ctx = NULL;
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if (!dev)
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return -EINVAL;
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priv = (struct he_mem_tg_priv *)dev->priv;
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if (!priv) {
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priv = rte_zmalloc(NULL, sizeof(struct he_mem_tg_priv), 0);
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if (!priv)
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return -ENOMEM;
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dev->priv = priv;
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}
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ctx = &priv->he_mem_tg_ctx;
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ctx->addr = (uint8_t *)dev->addr;
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return 0;
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}
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static int he_mem_tg_config(struct afu_rawdev *dev, void *config,
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size_t config_size)
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{
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struct he_mem_tg_priv *priv = NULL;
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if (!dev || !config || !config_size)
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return -EINVAL;
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priv = (struct he_mem_tg_priv *)dev->priv;
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if (!priv)
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return -ENOENT;
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if (config_size != sizeof(struct rte_pmd_afu_he_mem_tg_cfg))
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return -EINVAL;
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rte_memcpy(&priv->he_mem_tg_cfg, config, sizeof(priv->he_mem_tg_cfg));
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return 0;
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}
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static int he_mem_tg_close(struct afu_rawdev *dev)
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{
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if (!dev)
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return -EINVAL;
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rte_free(dev->priv);
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dev->priv = NULL;
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return 0;
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}
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static int he_mem_tg_dump(struct afu_rawdev *dev, FILE *f)
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{
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struct he_mem_tg_priv *priv = NULL;
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struct he_mem_tg_ctx *ctx = NULL;
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if (!dev)
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return -EINVAL;
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priv = (struct he_mem_tg_priv *)dev->priv;
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if (!priv)
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return -ENOENT;
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if (!f)
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f = stdout;
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ctx = &priv->he_mem_tg_ctx;
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fprintf(f, "addr:\t\t%p\n", (void *)ctx->addr);
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return 0;
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}
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static struct afu_ops he_mem_tg_ops = {
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.init = he_mem_tg_init,
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.config = he_mem_tg_config,
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.start = NULL,
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.stop = NULL,
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.test = he_mem_tg_test,
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.close = he_mem_tg_close,
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.dump = he_mem_tg_dump,
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.reset = NULL
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};
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struct afu_rawdev_drv he_mem_tg_drv = {
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.uuid = { HE_MEM_TG_UUID_L, HE_MEM_TG_UUID_H },
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.ops = &he_mem_tg_ops
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};
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AFU_PMD_REGISTER(he_mem_tg_drv);
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46
drivers/raw/ifpga/afu_pmd_he_mem.h
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46
drivers/raw/ifpga/afu_pmd_he_mem.h
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@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 Intel Corporation
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*/
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#ifndef AFU_PMD_HE_MEM_H
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#define AFU_PMD_HE_MEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "afu_pmd_core.h"
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#include "rte_pmd_afu.h"
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#define HE_MEM_TG_UUID_L 0xa3dc5b831f5cecbb
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#define HE_MEM_TG_UUID_H 0x4dadea342c7848cb
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#define NUM_MEM_TG_CHANNELS 4
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#define MEM_TG_TIMEOUT_MS 5000
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#define MEM_TG_POLL_INTERVAL_MS 10
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/* MEM-TG registers definition */
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#define MEM_TG_SCRATCHPAD 0x28
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#define MEM_TG_CTRL 0x30
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#define TGCONTROL(n) (1 << (n))
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#define MEM_TG_STAT 0x38
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#define TGSTATUS(v, n) (((v) >> (n << 2)) & 0xf)
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#define TGPASS(v, n) (((v) >> ((n << 2) + 3)) & 0x1)
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#define TGFAIL(v, n) (((v) >> ((n << 2) + 2)) & 0x1)
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#define TGTIMEOUT(v, n) (((v) >> ((n << 2) + 1)) & 0x1)
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#define TGACTIVE(v, n) (((v) >> (n << 2)) & 0x1)
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struct he_mem_tg_ctx {
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uint8_t *addr;
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};
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struct he_mem_tg_priv {
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struct rte_pmd_afu_he_mem_tg_cfg he_mem_tg_cfg;
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struct he_mem_tg_ctx he_mem_tg_ctx;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* AFU_PMD_HE_MEM_H */
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@ -14,7 +14,7 @@ deps += ['ethdev', 'rawdev', 'pci', 'bus_pci', 'kvargs',
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'bus_vdev', 'bus_ifpga', 'net', 'net_i40e', 'net_ipn3ke']
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sources = files('ifpga_rawdev.c', 'rte_pmd_ifpga.c', 'afu_pmd_core.c',
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'afu_pmd_n3000.c', 'afu_pmd_he_lpbk.c')
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'afu_pmd_n3000.c', 'afu_pmd_he_lpbk.c', 'afu_pmd_he_mem.c')
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includes += include_directories('base')
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includes += include_directories('../../net/ipn3ke')
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@ -104,6 +104,13 @@ struct rte_pmd_afu_he_lpbk_cfg {
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uint32_t freq_mhz;
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};
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/**
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* HE-MEM-TG AFU configuration data structure.
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*/
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struct rte_pmd_afu_he_mem_tg_cfg {
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uint32_t channel_mask; /* mask of traffic generator channel */
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};
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#ifdef __cplusplus
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}
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#endif
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