d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

raw/ntb: add PPD status check for Sapphire Rapids

Browse Source 
Add PPD (PCIe Port Definition) status check for SPR (Sapphire Rapids).

Note that NTB on SPR has the same device id with that on ICX, while
the field offsets of PPD Control Register are different. Here, we use
the PCI device revision id to distinguish the HW platform (ICX/SPR)
and check the Port Config Status and Port Definition accordingly.

+---------------------------+--------------------+--------------------+
|          Fields           | Bit Range (on ICX) | Bit Range (on SPR) |
+---------------------------+--------------------+--------------------+
| Port Configuration Status | 12                 | 14                 |
| Port Definition           | 9:8                | 10:8               |
+---------------------------+--------------------+--------------------+

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
This commit is contained in:
Junfeng Guo 2022-06-30 08:56:16 +00:00 committed by Thomas Monjalon
parent b29427649b
commit 834d99f388
3 changed files with 72 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/raw/ntb/ntb.h
View File

@ -19,6 +19,7 @@ extern int ntb_logtype;
/* Device IDs */
#define NTB_INTEL_DEV_ID_B2B_SKX 0x201C
#define NTB_INTEL_DEV_ID_B2B_ICX 0x347E
#define NTB_INTEL_DEV_ID_B2B_SPR 0x347E
/* Reserved to app to use. */
#define NTB_SPAD_USER "spad_user_"

64
drivers/raw/ntb/ntb_hw_intel.c
View File

@ -37,7 +37,8 @@ is_gen3_ntb(const struct ntb_hw *hw)
static inline int
is_gen4_ntb(const struct ntb_hw *hw)
{
if (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_ICX)
if (hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_ICX ||
hw->pci_dev->id.device_id == NTB_INTEL_DEV_ID_B2B_SPR)
return 1;
return 0;
@ -87,12 +88,8 @@ intel_ntb3_check_ppd(struct ntb_hw *hw)
}
static int
intel_ntb4_check_ppd(struct ntb_hw *hw)
intel_ntb4_check_ppd_for_ICX(struct ntb_hw *hw, uint32_t reg_val)
{
uint32_t reg_val;
reg_val = rte_read32(hw->hw_addr + XEON_GEN4_PPD1_OFFSET);
/* Check connection topo type. Only support B2B. */
switch (reg_val & XEON_GEN4_PPD_CONN_MASK) {
case XEON_GEN4_PPD_CONN_B2B:
@ -115,6 +112,61 @@ intel_ntb4_check_ppd(struct ntb_hw *hw)
return 0;
}
static int
intel_ntb4_check_ppd_for_SPR(struct ntb_hw *hw, uint32_t reg_val)
{
/* Check connection topo type. Only support B2B. */
switch (reg_val & XEON_SPR_PPD_CONN_MASK) {
case XEON_SPR_PPD_CONN_B2B:
NTB_LOG(INFO, "Topo B2B (back to back) is using.");
break;
default:
NTB_LOG(ERR, "Not supported conn topo. Please use B2B.");
return -EINVAL;
}
/* Check device type. */
if (reg_val & XEON_SPR_PPD_DEV_DSD) {
NTB_LOG(INFO, "DSD, Downstream Device.");
hw->topo = NTB_TOPO_B2B_DSD;
} else {
NTB_LOG(INFO, "USD, Upstream device.");
hw->topo = NTB_TOPO_B2B_USD;
}
return 0;
}
static int
intel_ntb4_check_ppd(struct ntb_hw *hw)
{
uint8_t revision_id;
uint32_t reg_val;
int ret;
ret = rte_pci_read_config(hw->pci_dev, &revision_id,
NTB_PCI_DEV_REVISION_ID_LEN,
NTB_PCI_DEV_REVISION_ID_REG);
if (ret != NTB_PCI_DEV_REVISION_ID_LEN) {
NTB_LOG(ERR, "Cannot get NTB PCI Device Revision ID.");
return -EIO;
}
reg_val = rte_read32(hw->hw_addr + XEON_GEN4_PPD1_OFFSET);
/* Distinguish HW platform (ICX/SPR) via PCI Revision ID */
if (revision_id > NTB_PCI_DEV_REVISION_ICX_MAX)
ret = intel_ntb4_check_ppd_for_SPR(hw, reg_val);
else if (revision_id >= NTB_PCI_DEV_REVISION_ICX_MIN)
ret = intel_ntb4_check_ppd_for_ICX(hw, reg_val);
else {
NTB_LOG(ERR, "Invalid NTB PCI Device Revision ID.");
return -EIO;
}
return ret;
}
static int
intel_ntb_dev_init(const struct rte_rawdev *dev)
{

13
drivers/raw/ntb/ntb_hw_intel.h
View File

@ -5,6 +5,13 @@
#ifndef _NTB_HW_INTEL_H_
#define _NTB_HW_INTEL_H_
/* Supported PCI device revision ID range for ICX */
#define NTB_PCI_DEV_REVISION_ICX_MIN 0x02
#define NTB_PCI_DEV_REVISION_ICX_MAX 0x0F
#define NTB_PCI_DEV_REVISION_ID_REG 0x08
#define NTB_PCI_DEV_REVISION_ID_LEN 1
/* Ntb control and link status */
#define NTB_CTL_CFG_LOCK 1
#define NTB_CTL_DISABLE 2
@ -90,6 +97,12 @@
#define XEON_GEN4_SLOTSTS 0xb05a
#define XEON_GEN4_SLOTSTS_DLLSCS 0x100
#define XEON_SPR_PPD_CONN_MASK 0x0700
#define XEON_SPR_PPD_CONN_B2B 0x0200
#define XEON_SPR_PPD_DEV_MASK 0x4000
#define XEON_SPR_PPD_DEV_DSD 0x4000
#define XEON_SPR_PPD_DEV_USD 0x0000
#define XEON_MW_COUNT 2
#define XEON_DB_COUNT 32