igb: support ieee1588 functions for device time
Add additional functions to support the existing IEEE1588 functionality and to enable getting, setting and adjusting the device time. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com> Reviewed-by: John McNamara <john.mcnamara@intel.com>
This commit is contained in:
Pablo de Lara
Thomas Monjalon
parent
1c4445e1f2
commit
9c857bf6be
@ -33,6 +33,7 @@
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#ifndef _E1000_ETHDEV_H_
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#define _E1000_ETHDEV_H_
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#include <rte_time.h>
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/* need update link, bit flag */
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#define E1000_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
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@ -257,6 +258,9 @@ struct e1000_adapter {
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struct e1000_vf_info *vfdata;
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struct e1000_filter_info filter;
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bool stopped;
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struct rte_timecounter systime_tc;
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struct rte_timecounter rx_tstamp_tc;
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struct rte_timecounter tx_tstamp_tc;
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};
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#define E1000_DEV_PRIVATE(adapter) \
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@ -78,10 +78,11 @@
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#define IGB_8_BIT_MASK UINT8_MAX
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/* Additional timesync values. */
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#define E1000_ETQF_FILTER_1588 3
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#define E1000_TIMINCA_INCVALUE 16000000
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#define E1000_TIMINCA_INIT ((0x02 << E1000_TIMINCA_16NS_SHIFT) \
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| E1000_TIMINCA_INCVALUE)
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#define E1000_CYCLECOUNTER_MASK 0xffffffffffffffff
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#define E1000_ETQF_FILTER_1588 3
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#define IGB_82576_TSYNC_SHIFT 16
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#define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
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#define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
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#define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
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static int eth_igb_configure(struct rte_eth_dev *dev);
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@ -236,6 +237,11 @@ static int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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uint32_t flags);
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static int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp);
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static int igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
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static int igb_timesync_read_time(struct rte_eth_dev *dev,
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struct timespec *timestamp);
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static int igb_timesync_write_time(struct rte_eth_dev *dev,
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const struct timespec *timestamp);
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static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
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uint16_t queue_id);
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static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
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@ -349,6 +355,9 @@ static const struct eth_dev_ops eth_igb_ops = {
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.get_eeprom_length = eth_igb_get_eeprom_length,
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.get_eeprom = eth_igb_get_eeprom,
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.set_eeprom = eth_igb_set_eeprom,
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.timesync_adjust_time = igb_timesync_adjust_time,
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.timesync_read_time = igb_timesync_read_time,
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.timesync_write_time = igb_timesync_write_time,
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};
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/*
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@ -4188,6 +4197,209 @@ eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,
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return 0;
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}
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static uint64_t
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igb_read_systime_cyclecounter(struct rte_eth_dev *dev)
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{
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struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t systime_cycles;
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switch (hw->mac.type) {
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case e1000_i210:
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case e1000_i211:
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/*
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* Need to read System Time Residue Register to be able
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* to read the other two registers.
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*/
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E1000_READ_REG(hw, E1000_SYSTIMR);
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/* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
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systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
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systime_cycles += (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
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* NSEC_PER_SEC;
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break;
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case e1000_82580:
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case e1000_i350:
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case e1000_i354:
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/*
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* Need to read System Time Residue Register to be able
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* to read the other two registers.
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*/
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E1000_READ_REG(hw, E1000_SYSTIMR);
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systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
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/* Only the 8 LSB are valid. */
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systime_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_SYSTIMH)
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& 0xff) << 32;
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break;
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default:
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systime_cycles = (uint64_t)E1000_READ_REG(hw, E1000_SYSTIML);
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systime_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_SYSTIMH)
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<< 32;
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break;
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}
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return systime_cycles;
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}
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static uint64_t
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igb_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
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{
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struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t rx_tstamp_cycles;
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switch (hw->mac.type) {
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case e1000_i210:
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case e1000_i211:
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/* RXSTMPL stores ns and RXSTMPH stores seconds. */
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rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
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rx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
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* NSEC_PER_SEC;
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break;
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case e1000_82580:
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case e1000_i350:
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case e1000_i354:
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rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
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/* Only the 8 LSB are valid. */
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rx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_RXSTMPH)
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& 0xff) << 32;
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break;
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default:
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rx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPL);
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rx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_RXSTMPH)
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<< 32;
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break;
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}
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return rx_tstamp_cycles;
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}
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static uint64_t
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igb_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
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{
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struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t tx_tstamp_cycles;
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switch (hw->mac.type) {
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case e1000_i210:
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case e1000_i211:
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/* RXSTMPL stores ns and RXSTMPH stores seconds. */
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tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
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tx_tstamp_cycles += (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
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* NSEC_PER_SEC;
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break;
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case e1000_82580:
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case e1000_i350:
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case e1000_i354:
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tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
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/* Only the 8 LSB are valid. */
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tx_tstamp_cycles |= (uint64_t)(E1000_READ_REG(hw, E1000_TXSTMPH)
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& 0xff) << 32;
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break;
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default:
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tx_tstamp_cycles = (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPL);
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tx_tstamp_cycles |= (uint64_t)E1000_READ_REG(hw, E1000_TXSTMPH)
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<< 32;
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break;
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}
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return tx_tstamp_cycles;
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}
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static void
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igb_start_timecounters(struct rte_eth_dev *dev)
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{
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struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct e1000_adapter *adapter =
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(struct e1000_adapter *)dev->data->dev_private;
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uint32_t incval = 1;
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uint32_t shift = 0;
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uint64_t mask = E1000_CYCLECOUNTER_MASK;
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switch (hw->mac.type) {
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case e1000_82580:
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case e1000_i350:
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case e1000_i354:
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/* 32 LSB bits + 8 MSB bits = 40 bits */
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mask = (1ULL << 40) - 1;
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/* fall-through */
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case e1000_i210:
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case e1000_i211:
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/*
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* Start incrementing the register
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* used to timestamp PTP packets.
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*/
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E1000_WRITE_REG(hw, E1000_TIMINCA, incval);
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break;
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case e1000_82576:
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incval = E1000_INCVALUE_82576;
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shift = IGB_82576_TSYNC_SHIFT;
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E1000_WRITE_REG(hw, E1000_TIMINCA,
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E1000_INCPERIOD_82576 | incval);
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break;
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default:
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/* Not supported */
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return;
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}
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memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
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memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
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memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
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adapter->systime_tc.cc_mask = mask;
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adapter->systime_tc.cc_shift = shift;
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adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
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adapter->rx_tstamp_tc.cc_mask = mask;
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adapter->rx_tstamp_tc.cc_shift = shift;
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adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
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adapter->tx_tstamp_tc.cc_mask = mask;
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adapter->tx_tstamp_tc.cc_shift = shift;
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adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
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}
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static int
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igb_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
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{
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struct e1000_adapter *adapter =
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(struct e1000_adapter *)dev->data->dev_private;
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adapter->systime_tc.nsec += delta;
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adapter->rx_tstamp_tc.nsec += delta;
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adapter->tx_tstamp_tc.nsec += delta;
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return 0;
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}
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static int
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igb_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
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{
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uint64_t ns;
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struct e1000_adapter *adapter =
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(struct e1000_adapter *)dev->data->dev_private;
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ns = rte_timespec_to_ns(ts);
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/* Set the timecounters to a new value. */
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adapter->systime_tc.nsec = ns;
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adapter->rx_tstamp_tc.nsec = ns;
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adapter->tx_tstamp_tc.nsec = ns;
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return 0;
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}
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static int
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igb_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
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{
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uint64_t ns, systime_cycles;
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struct e1000_adapter *adapter =
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(struct e1000_adapter *)dev->data->dev_private;
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systime_cycles = igb_read_systime_cyclecounter(dev);
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ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
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*ts = rte_ns_to_timespec(ns);
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return 0;
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}
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static int
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igb_timesync_enable(struct rte_eth_dev *dev)
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{
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@ -4195,13 +4407,32 @@ igb_timesync_enable(struct rte_eth_dev *dev)
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uint32_t tsync_ctl;
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uint32_t tsauxc;
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/* Stop the timesync system time. */
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E1000_WRITE_REG(hw, E1000_TIMINCA, 0x0);
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/* Reset the timesync system time value. */
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switch (hw->mac.type) {
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case e1000_82580:
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case e1000_i350:
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case e1000_i354:
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case e1000_i210:
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case e1000_i211:
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E1000_WRITE_REG(hw, E1000_SYSTIMR, 0x0);
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/* fall-through */
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case e1000_82576:
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E1000_WRITE_REG(hw, E1000_SYSTIML, 0x0);
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E1000_WRITE_REG(hw, E1000_SYSTIMH, 0x0);
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break;
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default:
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/* Not supported. */
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return -ENOTSUP;
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}
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/* Enable system time for it isn't on by default. */
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tsauxc = E1000_READ_REG(hw, E1000_TSAUXC);
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tsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;
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E1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);
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/* Start incrementing the register used to timestamp PTP packets. */
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E1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);
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igb_start_timecounters(dev);
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/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
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E1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),
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@ -4253,19 +4484,19 @@ igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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uint32_t flags __rte_unused)
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{
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struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct e1000_adapter *adapter =
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(struct e1000_adapter *)dev->data->dev_private;
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uint32_t tsync_rxctl;
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uint32_t rx_stmpl;
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uint32_t rx_stmph;
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uint64_t rx_tstamp_cycles;
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uint64_t ns;
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tsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);
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if ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)
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return -EINVAL;
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rx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);
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rx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);
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timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
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timestamp->tv_nsec = 0;
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rx_tstamp_cycles = igb_read_rx_tstamp_cyclecounter(dev);
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ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
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*timestamp = rte_ns_to_timespec(ns);
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return 0;
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}
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@ -4275,19 +4506,19 @@ igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp)
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{
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struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct e1000_adapter *adapter =
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(struct e1000_adapter *)dev->data->dev_private;
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uint32_t tsync_txctl;
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uint32_t tx_stmpl;
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uint32_t tx_stmph;
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uint64_t tx_tstamp_cycles;
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uint64_t ns;
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tsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);
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if ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)
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return -EINVAL;
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tx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);
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tx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);
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timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
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timestamp->tv_nsec = 0;
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tx_tstamp_cycles = igb_read_tx_tstamp_cyclecounter(dev);
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ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
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*timestamp = rte_ns_to_timespec(ns);
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return 0;
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}
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