dma/hisilicon: add probing
This patch add dmadev instances create during the PCI probe, and destroy them during the PCI remove. Internal structures and HW definitions was also included. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
This commit is contained in:
Chengwen Feng
Thomas Monjalon
parent
4d0d4cf327
commit
9e16317a38
@ -20,3 +20,14 @@ Device Setup
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Kunpeng DMA devices will need to be bound to a suitable DPDK-supported
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user-space IO driver such as ``vfio-pci`` in order to be used by DPDK.
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Device Probing and Initialization
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Once probed successfully, the device will appear as four ``dmadev``
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which can be accessed using API from the ``rte_dmadev`` library.
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The name of the ``dmadev`` created is like "B:D.F-chX", e.g. DMA 0000:7b:00.0
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will create four ``dmadev``,
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the 1st ``dmadev`` name is "7b:00.0-ch0",
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and the 2nd ``dmadev`` name is "7b:00.0-ch1".
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@ -6,7 +6,9 @@
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#include <string.h>
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#include <rte_bus_pci.h>
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#include <rte_cycles.h>
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#include <rte_eal.h>
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#include <rte_io.h>
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#include <rte_log.h>
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#include <rte_pci.h>
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#include <rte_dmadev_pmd.h>
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@ -30,6 +32,141 @@ RTE_LOG_REGISTER_DEFAULT(hisi_dma_logtype, INFO);
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#define HISI_DMA_ERR(hw, fmt, args...) \
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HISI_DMA_LOG_RAW(hw, ERR, fmt, ## args)
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static uint32_t
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hisi_dma_queue_base(struct hisi_dma_dev *hw)
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{
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if (hw->reg_layout == HISI_DMA_REG_LAYOUT_HIP08)
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return HISI_DMA_HIP08_QUEUE_BASE;
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else
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return 0;
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}
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static void
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hisi_dma_write_reg(void *base, uint32_t off, uint32_t val)
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{
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rte_write32(rte_cpu_to_le_32(val),
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(volatile void *)((char *)base + off));
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}
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static void
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hisi_dma_write_dev(struct hisi_dma_dev *hw, uint32_t off, uint32_t val)
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{
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hisi_dma_write_reg(hw->io_base, off, val);
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}
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static void
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hisi_dma_write_queue(struct hisi_dma_dev *hw, uint32_t qoff, uint32_t val)
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{
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uint32_t off = hisi_dma_queue_base(hw) +
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hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
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hisi_dma_write_dev(hw, off, val);
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}
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static uint32_t
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hisi_dma_read_reg(void *base, uint32_t off)
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{
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uint32_t val = rte_read32((volatile void *)((char *)base + off));
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return rte_le_to_cpu_32(val);
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}
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static uint32_t
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hisi_dma_read_dev(struct hisi_dma_dev *hw, uint32_t off)
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{
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return hisi_dma_read_reg(hw->io_base, off);
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}
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static uint32_t
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hisi_dma_read_queue(struct hisi_dma_dev *hw, uint32_t qoff)
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{
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uint32_t off = hisi_dma_queue_base(hw) +
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hw->queue_id * HISI_DMA_QUEUE_REGION_SIZE + qoff;
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return hisi_dma_read_dev(hw, off);
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}
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static void
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hisi_dma_update_bit(struct hisi_dma_dev *hw, uint32_t off, uint32_t pos,
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bool set)
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{
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uint32_t tmp = hisi_dma_read_dev(hw, off);
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uint32_t mask = 1u << pos;
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tmp = set ? tmp | mask : tmp & ~mask;
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hisi_dma_write_dev(hw, off, tmp);
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}
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static void
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hisi_dma_update_queue_bit(struct hisi_dma_dev *hw, uint32_t qoff, uint32_t pos,
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bool set)
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{
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uint32_t tmp = hisi_dma_read_queue(hw, qoff);
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uint32_t mask = 1u << pos;
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tmp = set ? tmp | mask : tmp & ~mask;
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hisi_dma_write_queue(hw, qoff, tmp);
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}
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#define hisi_dma_poll_hw_state(hw, val, cond, sleep_us, timeout_us) ({ \
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uint32_t timeout = 0; \
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while (timeout++ <= (timeout_us)) { \
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(val) = hisi_dma_read_queue(hw, HISI_DMA_QUEUE_FSM_REG); \
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if (cond) \
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break; \
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rte_delay_us(sleep_us); \
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} \
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(cond) ? 0 : -ETIME; \
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})
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static int
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hisi_dma_reset_hw(struct hisi_dma_dev *hw)
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{
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#define POLL_SLEEP_US 100
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#define POLL_TIMEOUT_US 10000
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uint32_t tmp;
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int ret;
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hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
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HISI_DMA_QUEUE_CTRL0_PAUSE_B, true);
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hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
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HISI_DMA_QUEUE_CTRL0_EN_B, false);
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ret = hisi_dma_poll_hw_state(hw, tmp,
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FIELD_GET(HISI_DMA_QUEUE_FSM_STS_M, tmp) != HISI_DMA_STATE_RUN,
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POLL_SLEEP_US, POLL_TIMEOUT_US);
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if (ret) {
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HISI_DMA_ERR(hw, "disable dma timeout!");
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return ret;
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}
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hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL1_REG,
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HISI_DMA_QUEUE_CTRL1_RESET_B, true);
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hisi_dma_write_queue(hw, HISI_DMA_QUEUE_SQ_TAIL_REG, 0);
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hisi_dma_write_queue(hw, HISI_DMA_QUEUE_CQ_HEAD_REG, 0);
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hisi_dma_update_queue_bit(hw, HISI_DMA_QUEUE_CTRL0_REG,
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HISI_DMA_QUEUE_CTRL0_PAUSE_B, false);
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ret = hisi_dma_poll_hw_state(hw, tmp,
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FIELD_GET(HISI_DMA_QUEUE_FSM_STS_M, tmp) == HISI_DMA_STATE_IDLE,
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POLL_SLEEP_US, POLL_TIMEOUT_US);
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if (ret) {
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HISI_DMA_ERR(hw, "reset dma timeout!");
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return ret;
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}
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return 0;
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}
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static void
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hisi_dma_init_gbl(void *pci_bar, uint8_t revision)
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{
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struct hisi_dma_dev hw;
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memset(&hw, 0, sizeof(hw));
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hw.io_base = pci_bar;
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if (revision == HISI_DMA_REVISION_HIP08B)
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hisi_dma_update_bit(&hw, HISI_DMA_HIP08_MODE_REG,
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HISI_DMA_HIP08_MODE_SEL_B, true);
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}
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static uint8_t
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hisi_dma_reg_layout(uint8_t revision)
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{
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@ -49,6 +186,57 @@ hisi_dma_gen_pci_device_name(const struct rte_pci_device *pci_dev,
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pci_dev->addr.function);
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}
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static void
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hisi_dma_gen_dev_name(const struct rte_pci_device *pci_dev,
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uint8_t queue_id, char *name, size_t size)
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{
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memset(name, 0, size);
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(void)snprintf(name, size, "%x:%x.%x-ch%u",
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pci_dev->addr.bus, pci_dev->addr.devid,
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pci_dev->addr.function, queue_id);
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}
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static int
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hisi_dma_create(struct rte_pci_device *pci_dev, uint8_t queue_id,
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uint8_t revision)
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{
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#define REG_PCI_BAR_INDEX 2
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char name[RTE_DEV_NAME_MAX_LEN];
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struct rte_dma_dev *dev;
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struct hisi_dma_dev *hw;
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int ret;
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hisi_dma_gen_dev_name(pci_dev, queue_id, name, sizeof(name));
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dev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node,
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sizeof(*hw));
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if (dev == NULL) {
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HISI_DMA_LOG(ERR, "%s allocate dmadev fail!", name);
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return -EINVAL;
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}
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dev->device = &pci_dev->device;
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hw = dev->data->dev_private;
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hw->data = dev->data;
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hw->revision = revision;
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hw->reg_layout = hisi_dma_reg_layout(revision);
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hw->io_base = pci_dev->mem_resource[REG_PCI_BAR_INDEX].addr;
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hw->queue_id = queue_id;
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ret = hisi_dma_reset_hw(hw);
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if (ret) {
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HISI_DMA_LOG(ERR, "%s init device fail!", name);
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(void)rte_dma_pmd_release(name);
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return -EIO;
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}
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dev->state = RTE_DMA_DEV_READY;
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HISI_DMA_LOG(DEBUG, "%s create dmadev success!", name);
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return 0;
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}
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static int
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hisi_dma_check_revision(struct rte_pci_device *pci_dev, const char *name,
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uint8_t *out_revision)
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@ -78,6 +266,7 @@ hisi_dma_probe(struct rte_pci_driver *pci_drv __rte_unused,
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{
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char name[RTE_DEV_NAME_MAX_LEN] = { 0 };
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uint8_t revision;
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uint8_t i;
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int ret;
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hisi_dma_gen_pci_device_name(pci_dev, name, sizeof(name));
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@ -92,13 +281,34 @@ hisi_dma_probe(struct rte_pci_driver *pci_drv __rte_unused,
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return ret;
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HISI_DMA_LOG(DEBUG, "%s read PCI revision: 0x%x", name, revision);
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hisi_dma_init_gbl(pci_dev->mem_resource[2].addr, revision);
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for (i = 0; i < HISI_DMA_MAX_HW_QUEUES; i++) {
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ret = hisi_dma_create(pci_dev, i, revision);
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if (ret) {
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HISI_DMA_LOG(ERR, "%s create dmadev %u failed!",
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name, i);
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break;
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}
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}
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return ret;
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}
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static int
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hisi_dma_remove(struct rte_pci_device *pci_dev)
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{
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RTE_SET_USED(pci_dev);
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char name[RTE_DEV_NAME_MAX_LEN];
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uint8_t i;
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int ret;
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for (i = 0; i < HISI_DMA_MAX_HW_QUEUES; i++) {
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hisi_dma_gen_dev_name(pci_dev, i, name, sizeof(name));
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ret = rte_dma_pmd_release(name);
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if (ret)
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return ret;
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}
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return 0;
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}
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@ -5,11 +5,24 @@
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#ifndef HISI_DMADEV_H
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#define HISI_DMADEV_H
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#include <rte_byteorder.h>
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#include <rte_common.h>
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#define BIT(x) (1ul << (x))
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#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
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#define GENMASK(h, l) \
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(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
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#define BF_SHF(x) (__builtin_ffsll(x) - 1)
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#define FIELD_GET(mask, reg) \
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((typeof(mask))(((reg) & (mask)) >> BF_SHF(mask)))
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#define PCI_VENDOR_ID_HUAWEI 0x19e5
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#define HISI_DMA_DEVICE_ID 0xA122
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#define HISI_DMA_PCI_REVISION_ID_REG 0x08
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#define HISI_DMA_REVISION_HIP08B 0x21
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#define HISI_DMA_MAX_HW_QUEUES 4
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/**
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* The HIP08B(HiSilicon IP08) and later Chip(e.g. HiSilicon IP09) are DMA iEPs,
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* they have the same pci device id but with different pci revision.
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@ -21,4 +34,88 @@ enum {
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HISI_DMA_REG_LAYOUT_HIP08
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};
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/**
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* Hardware PCI bar register MAP:
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*
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* --------------
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* | Misc-reg-0 |
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* | |
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* -------------- -> Queue base
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* | |
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* | Queue-0 |
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* | |
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* -------------- ---
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* | | ^
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* | Queue-1 | Queue region
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* | | v
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* -------------- ---
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* | ... |
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* | Queue-x |
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* | ... |
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* --------------
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* | Misc-reg-1 |
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* --------------
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*
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* As described above, a single queue register is continuous and occupies the
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* length of queue-region. The global offset for a single queue register is
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* calculated by:
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* offset = queue-base + (queue-id * queue-region) + reg-offset-in-region.
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*
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* The first part of queue region is basically the same for HIP08 and later chip
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* register layouts, therefore, HISI_QUEUE_* registers are defined for it.
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*/
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#define HISI_DMA_QUEUE_SQ_BASE_L_REG 0x0
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#define HISI_DMA_QUEUE_SQ_BASE_H_REG 0x4
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#define HISI_DMA_QUEUE_SQ_DEPTH_REG 0x8
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#define HISI_DMA_QUEUE_SQ_TAIL_REG 0xC
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#define HISI_DMA_QUEUE_CQ_BASE_L_REG 0x10
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#define HISI_DMA_QUEUE_CQ_BASE_H_REG 0x14
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#define HISI_DMA_QUEUE_CQ_DEPTH_REG 0x18
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#define HISI_DMA_QUEUE_CQ_HEAD_REG 0x1C
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#define HISI_DMA_QUEUE_CTRL0_REG 0x20
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#define HISI_DMA_QUEUE_CTRL0_EN_B 0
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#define HISI_DMA_QUEUE_CTRL0_PAUSE_B 4
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#define HISI_DMA_QUEUE_CTRL1_REG 0x24
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#define HISI_DMA_QUEUE_CTRL1_RESET_B 0
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#define HISI_DMA_QUEUE_FSM_REG 0x30
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#define HISI_DMA_QUEUE_FSM_STS_M GENMASK(3, 0)
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#define HISI_DMA_QUEUE_INT_STATUS_REG 0x40
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#define HISI_DMA_QUEUE_ERR_INT_NUM0_REG 0x84
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#define HISI_DMA_QUEUE_ERR_INT_NUM1_REG 0x88
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#define HISI_DMA_QUEUE_ERR_INT_NUM2_REG 0x8C
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#define HISI_DMA_QUEUE_REGION_SIZE 0x100
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/**
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* HiSilicon IP08 DMA register and field define:
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*/
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#define HISI_DMA_HIP08_QUEUE_BASE 0x0
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#define HISI_DMA_HIP08_QUEUE_CTRL0_ERR_ABORT_B 2
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#define HISI_DMA_HIP08_QUEUE_INT_MASK_REG 0x44
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#define HISI_DMA_HIP08_QUEUE_INT_MASK_M GENMASK(14, 0)
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#define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM3_REG 0x90
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#define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM4_REG 0x94
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#define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM5_REG 0x98
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#define HISI_DMA_HIP08_QUEUE_ERR_INT_NUM6_REG 0x48
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#define HISI_DMA_HIP08_MODE_REG 0x217C
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#define HISI_DMA_HIP08_MODE_SEL_B 0
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#define HISI_DMA_HIP08_DUMP_START_REG 0x2000
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#define HISI_DMA_HIP08_DUMP_END_REG 0x2280
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/**
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* In fact, there are multiple states, but it need to pay attention to
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* the following two states for the driver:
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*/
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enum {
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HISI_DMA_STATE_IDLE = 0,
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HISI_DMA_STATE_RUN,
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};
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struct hisi_dma_dev {
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struct rte_dma_dev_data *data;
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uint8_t revision; /**< PCI revision. */
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uint8_t reg_layout; /**< hardware register layout. */
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void *io_base;
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uint8_t queue_id; /**< hardware DMA queue index. */
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};
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#endif /* HISI_DMADEV_H */
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