common/cnxk: add soft expiry poll frequency argument
Add support to override soft expiry poll frequency via devargs.
Also provide helper API to indicate reassembly support on a chip
and documentation for devargs that are already present.
Fixes: 780b9c8924
("net/cnxk: support zero AURA for inline meta")
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
This commit is contained in:
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@ -494,6 +494,45 @@ Runtime Config Options for inline device
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With the above configuration, application can enable inline IPsec processing
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for inbound SA with max SPI of 128 for traffic aggregated on inline device.
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- ``Count of meta buffers for inline inbound IPsec second pass``
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Number of meta buffers allocated for inline inbound IPsec second pass can
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be specified by ``nb_meta_bufs`` ``devargs`` parameter. Default value is
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computed runtime based on pkt mbuf pools created and in use. Number of meta
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buffers should be at least equal to aggregated number of packet buffers of all
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packet mbuf pools in use by Inline IPsec enabled ethernet devices.
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For example::
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-a 0002:1d:00.0,nb_meta_bufs=1024
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With the above configuration, PMD would enable inline IPsec processing
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for inbound with 1024 meta buffers available for second pass.
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- ``Meta buffer size for inline inbound IPsec second pass``
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Size of meta buffer allocated for inline inbound IPsec second pass can
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be specified by ``meta_buf_sz`` ``devargs`` parameter. Default value is
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computed runtime based on pkt mbuf pools created and in use.
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For example::
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-a 0002:1d:00.0,meta_buf_sz=512
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With the above configuration, PMD would allocate meta buffers of size 512 for
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inline inbound IPsec processing second pass.
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- ``Inline Outbound soft expiry poll frequency in usec`` (default ``100``)
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Soft expiry poll frequency for Inline Outbound sessions can be specified by
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``soft_exp_poll_freq`` ``devargs`` parameter.
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For example::
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-a 0002:1d:00.0,soft_exp_poll_freq=1000
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With the above configuration, driver would poll for soft expiry events every
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1000 usec.
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Debugging Options
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-----------------
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@ -480,6 +480,13 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)
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return mbox_process(mbox);
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}
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bool
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roc_nix_has_reass_support(struct roc_nix *nix)
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{
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PLT_SET_USED(nix);
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return !!roc_model_is_cn10ka();
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}
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int
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roc_nix_inl_inb_init(struct roc_nix *roc_nix)
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{
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@ -183,7 +183,7 @@ struct roc_nix_inl_dev {
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uint16_t wqe_skip;
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uint8_t spb_drop_pc;
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uint8_t lpb_drop_pc;
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bool set_soft_exp_poll;
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uint32_t soft_exp_poll_freq; /* Polling disabled if 0 */
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uint32_t nb_meta_bufs;
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uint32_t meta_buf_sz;
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/* End of input parameters */
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@ -229,6 +229,7 @@ int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena,
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bool inb_inl_dev);
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int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena);
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int __roc_api roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq);
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bool __roc_api roc_nix_has_reass_support(struct roc_nix *nix);
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/* NIX Inline Outbound API */
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int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix);
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@ -789,7 +789,6 @@ nix_inl_outb_poll_thread_setup(struct nix_inl_dev *inl_dev)
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soft_exp_consumer_cnt = 0;
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soft_exp_poll_thread_exit = false;
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inl_dev->soft_exp_poll_freq = 100;
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rc = plt_ctrl_thread_create(&inl_dev->soft_exp_poll_thread,
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"OUTB_SOFT_EXP_POLL_THREAD", NULL,
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nix_inl_outb_poll_thread, inl_dev);
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@ -839,10 +838,11 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
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inl_dev->wqe_skip = roc_inl_dev->wqe_skip;
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inl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT;
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inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;
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inl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll;
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inl_dev->set_soft_exp_poll = !!roc_inl_dev->soft_exp_poll_freq;
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inl_dev->nb_rqs = inl_dev->is_multi_channel ? 1 : PLT_MAX_ETHPORTS;
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inl_dev->nb_meta_bufs = roc_inl_dev->nb_meta_bufs;
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inl_dev->meta_buf_sz = roc_inl_dev->meta_buf_sz;
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inl_dev->soft_exp_poll_freq = roc_inl_dev->soft_exp_poll_freq;
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if (roc_inl_dev->spb_drop_pc)
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inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;
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@ -135,6 +135,7 @@ INTERNAL {
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roc_nix_get_pf_func;
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roc_nix_get_vf;
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roc_nix_get_vwqe_interval;
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roc_nix_has_reass_support;
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roc_nix_inl_cb_register;
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roc_nix_inl_cb_unregister;
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roc_nix_inl_ctx_write;
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@ -12,6 +12,10 @@
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#define CNXK_INL_CPT_CHANNEL "inl_cpt_channel"
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#define CNXK_NIX_INL_NB_META_BUFS "nb_meta_bufs"
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#define CNXK_NIX_INL_META_BUF_SZ "meta_buf_sz"
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#define CNXK_NIX_SOFT_EXP_POLL_FREQ "soft_exp_poll_freq"
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/* Default soft expiry poll freq in usec */
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#define CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT 100
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struct inl_cpt_channel {
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bool is_multi_channel;
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@ -263,6 +267,7 @@ static int
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nix_inl_parse_devargs(struct rte_devargs *devargs,
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struct roc_nix_inl_dev *inl_dev)
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{
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uint32_t soft_exp_poll_freq = CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT;
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uint32_t ipsec_in_max_spi = BIT(8) - 1;
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uint32_t ipsec_in_min_spi = 0;
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struct inl_cpt_channel cpt_channel;
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@ -292,6 +297,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
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&nb_meta_bufs);
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rte_kvargs_process(kvlist, CNXK_NIX_INL_META_BUF_SZ, &parse_val_u32,
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&meta_buf_sz);
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rte_kvargs_process(kvlist, CNXK_NIX_SOFT_EXP_POLL_FREQ,
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&parse_val_u32, &soft_exp_poll_freq);
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rte_kvargs_free(kvlist);
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null_devargs:
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@ -303,6 +310,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
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inl_dev->is_multi_channel = cpt_channel.is_multi_channel;
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inl_dev->nb_meta_bufs = nb_meta_bufs;
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inl_dev->meta_buf_sz = meta_buf_sz;
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inl_dev->soft_exp_poll_freq = soft_exp_poll_freq;
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return 0;
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exit:
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return -EINVAL;
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@ -390,7 +398,6 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv,
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wqe_skip = RTE_ALIGN_CEIL(sizeof(struct rte_mbuf), ROC_CACHE_LINE_SZ);
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wqe_skip = wqe_skip / ROC_CACHE_LINE_SZ;
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inl_dev->wqe_skip = wqe_skip;
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inl_dev->set_soft_exp_poll = true;
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rc = roc_nix_inl_dev_init(inl_dev);
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if (rc) {
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plt_err("Failed to init nix inl device, rc=%d(%s)", rc,
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@ -425,5 +432,9 @@ RTE_PMD_REGISTER_KMOD_DEP(cnxk_nix_inl, "vfio-pci");
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RTE_PMD_REGISTER_PARAM_STRING(cnxk_nix_inl,
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CNXK_NIX_INL_SELFTEST "=1"
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CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-65535>"
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CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>");
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CNXK_NIX_INL_IPSEC_IN_MIN_SPI "=<1-U32_MAX>"
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CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-U32_MAX>"
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CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>"
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CNXK_NIX_INL_NB_META_BUFS "=<1-U32_MAX>"
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CNXK_NIX_INL_META_BUF_SZ "=<1-U32_MAX>"
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CNXK_NIX_SOFT_EXP_POLL_FREQ "=<0-U32_MAX>");
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