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net/octeontx2: handle device error interrupts

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Handle device specific error and ras interrupts.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
This commit is contained in:
Jerin Jacob 2019-05-28 19:50:07 +05:30 committed by Ferruh Yigit
parent fb0198b7dc
commit b26d65bee9
5 changed files with 156 additions and 2 deletions
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1
drivers/net/octeontx2/Makefile
View File

@ -33,6 +33,7 @@ LIBABIVER := 1
SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \
otx2_mac.c \
otx2_ethdev.c \
otx2_ethdev_irq.c \
otx2_ethdev_devargs.c
LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2 -lrte_eal

1
drivers/net/octeontx2/meson.build
View File

@ -5,6 +5,7 @@
sources = files(
'otx2_mac.c',
'otx2_ethdev.c',
'otx2_ethdev_irq.c',
'otx2_ethdev_devargs.c'
)

12
drivers/net/octeontx2/otx2_ethdev.c
View File

@ -175,12 +175,17 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
if (rc)
goto otx2_npa_uninit;
/* Register LF irq handlers */
rc = otx2_nix_register_irqs(eth_dev);
if (rc)
goto mbox_detach;
/* Get maximum number of supported MAC entries */
max_entries = otx2_cgx_mac_max_entries_get(dev);
if (max_entries < 0) {
otx2_err("Failed to get max entries for mac addr");
rc = -ENOTSUP;
goto mbox_detach;
goto unregister_irq;
}
/* For VFs, returned max_entries will be 0. But to keep default MAC
@ -194,7 +199,7 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
if (eth_dev->data->mac_addrs == NULL) {
otx2_err("Failed to allocate memory for mac addr");
rc = -ENOMEM;
goto mbox_detach;
goto unregister_irq;
}
dev->max_mac_entries = max_entries;
@ -226,6 +231,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
free_mac_addrs:
rte_free(eth_dev->data->mac_addrs);
unregister_irq:
otx2_nix_unregister_irqs(eth_dev);
mbox_detach:
otx2_eth_dev_lf_detach(dev->mbox);
otx2_npa_uninit:
@ -261,6 +268,7 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
dev->drv_inited = false;
pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
otx2_nix_unregister_irqs(eth_dev);
rc = otx2_eth_dev_lf_detach(dev->mbox);
if (rc)

4
drivers/net/octeontx2/otx2_ethdev.h
View File

@ -105,6 +105,10 @@ otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
return eth_dev->data->dev_private;
}
/* IRQ */
int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
/* CGX */
int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);

140
drivers/net/octeontx2/otx2_ethdev_irq.c Normal file
View File

@ -0,0 +1,140 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(C) 2019 Marvell International Ltd.
*/
#include <inttypes.h>
#include <rte_bus_pci.h>
#include "otx2_ethdev.h"
static void
nix_lf_err_irq(void *param)
{
struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
uint64_t intr;
intr = otx2_read64(dev->base + NIX_LF_ERR_INT);
if (intr == 0)
return;
otx2_err("Err_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
/* Clear interrupt */
otx2_write64(intr, dev->base + NIX_LF_ERR_INT);
}
static int
nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
struct rte_intr_handle *handle = &pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int rc, vec;
vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
/* Clear err interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
/* Set used interrupt vectors */
rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);
/* Enable all dev interrupt except for RQ_DISABLED */
otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
return rc;
}
static void
nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
struct rte_intr_handle *handle = &pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec;
vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
/* Clear err interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);
}
static void
nix_lf_ras_irq(void *param)
{
struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
uint64_t intr;
intr = otx2_read64(dev->base + NIX_LF_RAS);
if (intr == 0)
return;
otx2_err("Ras_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
/* Clear interrupt */
otx2_write64(intr, dev->base + NIX_LF_RAS);
}
static int
nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
struct rte_intr_handle *handle = &pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int rc, vec;
vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
/* Clear err interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
/* Set used interrupt vectors */
rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);
/* Enable dev interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
return rc;
}
static void
nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
struct rte_intr_handle *handle = &pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec;
vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
/* Clear err interrupt */
otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);
}
int
otx2_nix_register_irqs(struct rte_eth_dev *eth_dev)
{
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int rc;
if (dev->nix_msixoff == MSIX_VECTOR_INVALID) {
otx2_err("Invalid NIXLF MSIX vector offset vector: 0x%x",
dev->nix_msixoff);
return -EINVAL;
}
/* Register lf err interrupt */
rc = nix_lf_register_err_irq(eth_dev);
/* Register RAS interrupt */
rc |= nix_lf_register_ras_irq(eth_dev);
return rc;
}
void
otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev)
{
nix_lf_unregister_err_irq(eth_dev);
nix_lf_unregister_ras_irq(eth_dev);
}