net/bnxt: remove unused macros and fields
Remove unused structure fields and macro definitions. Signed-off-by: Lance Richardson <lance.richardson@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
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@ -20,19 +20,14 @@ struct bnxt_rx_queue {
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* and fast path
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*/
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struct rte_mempool *mb_pool; /* mbuf pool for RX ring */
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struct rte_mbuf *pkt_first_seg; /* 1st seg of pkt */
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struct rte_mbuf *pkt_last_seg; /* Last seg of pkt */
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uint64_t mbuf_initializer; /* val to init mbuf */
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uint16_t nb_rx_desc; /* num of RX desc */
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uint16_t rx_tail; /* cur val of RDT register */
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uint16_t nb_rx_hold; /* num held free RX desc */
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uint16_t rx_free_thresh; /* max free RX desc to hold */
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uint16_t queue_id; /* RX queue index */
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#if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
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uint16_t rxrearm_nb; /* number of descs to reinit. */
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uint16_t rxrearm_start; /* next desc index to reinit. */
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#endif
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uint16_t reg_idx; /* RX queue register index */
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uint16_t port_id; /* Device port identifier */
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uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
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uint8_t rx_deferred_start; /* not in global dev start */
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@ -7,110 +7,6 @@
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#define _BNXT_RXR_H_
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#include "hsi_struct_def_dpdk.h"
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#define B_RX_DB(db, prod) \
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(*(uint32_t *)db = (DB_KEY_RX | (prod)))
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#define BNXT_TPA_L4_SIZE(x) \
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{ \
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typeof(x) hdr_info = (x); \
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(((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) \
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}
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#define BNXT_TPA_INNER_L3_OFF(hdr_info) \
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(((hdr_info) >> 18) & 0x1ff)
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#define BNXT_TPA_INNER_L2_OFF(hdr_info) \
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(((hdr_info) >> 9) & 0x1ff)
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#define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
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((hdr_info) & 0x1ff)
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#define flags2_0xf(rxcmp1) \
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(((rxcmp1)->flags2) & 0xf)
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/* IP non tunnel can be with or without L4-
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* Ether / (vlan) / IP|IP6 / UDP|TCP|SCTP Or
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* Ether / (vlan) / outer IP|IP6 / ICMP
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* we use '==' instead of '&' because tunnel pkts have all 4 fields set.
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*/
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#define IS_IP_NONTUNNEL_PKT(flags2_f) \
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( \
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((flags2_f) == \
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(rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC))) || \
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((flags2_f) == \
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(rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
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RX_PKT_CMPL_FLAGS2_L4_CS_CALC))) \
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)
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/* IP Tunnel pkt must have atleast tunnel-IP-calc set.
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* again tunnel ie outer L4 is optional bcoz of
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* Ether / (vlan) / outer IP|IP6 / GRE / Ether / IP|IP6 / UDP|TCP|SCTP
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* Ether / (vlan) / outer IP|IP6 / outer UDP / VxLAN / Ether / IP|IP6 /
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* UDP|TCP|SCTP
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* Ether / (vlan) / outer IP|IP6 / outer UDP / VXLAN-GPE / Ether / IP|IP6 /
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* UDP|TCP|SCTP
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* Ether / (vlan) / outer IP|IP6 / outer UDP / VXLAN-GPE / IP|IP6 /
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* UDP|TCP|SCTP
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* Ether / (vlan) / outer IP|IP6 / GRE / IP|IP6 / UDP|TCP|SCTP
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* Ether / (vlan) / outer IP|IP6 / IP|IP6 / UDP|TCP|SCTP
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* also inner L3 chksum error is not taken into consideration by DPDK.
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*/
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#define IS_IP_TUNNEL_PKT(flags2_f) \
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((flags2_f) & rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC))
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/* RX_PKT_CMPL_ERRORS_IP_CS_ERROR only for Non-tunnel pkts.
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* For tunnel pkts RX_PKT_CMPL_ERRORS_IP_CS_ERROR is not accounted and treated
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* as good csum pkt.
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*/
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#define RX_CMP_IP_CS_ERROR(rxcmp1) \
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((rxcmp1)->errors_v2 & \
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rte_cpu_to_le_32(RX_PKT_CMPL_ERRORS_IP_CS_ERROR))
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#define RX_CMP_IP_OUTER_CS_ERROR(rxcmp1) \
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((rxcmp1)->errors_v2 & \
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rte_cpu_to_le_32(RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR))
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#define RX_CMP_IP_CS_BITS \
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rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
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RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)
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#define RX_CMP_IP_CS_UNKNOWN(rxcmp1) \
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!((rxcmp1)->flags2 & RX_CMP_IP_CS_BITS)
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/* L4 non tunnel pkt-
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* Ether / (vlan) / IP6 / UDP|TCP|SCTP
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*/
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#define IS_L4_NONTUNNEL_PKT(flags2_f) \
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( \
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((flags2_f) == \
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(rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
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RX_PKT_CMPL_FLAGS2_L4_CS_CALC))))
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/* L4 tunnel pkt-
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* Outer L4 is not mandatory. Eg: GRE-
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* Ether / (vlan) / outer IP|IP6 / GRE / Ether / IP|IP6 / UDP|TCP|SCTP
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* Ether / (vlan) / outer IP|IP6 / outer UDP / VxLAN / Ether / IP|IP6 /
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* UDP|TCP|SCTP
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*/
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#define IS_L4_TUNNEL_PKT_INNER_OUTER_L4_CS(flags2_f) \
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((flags2_f) == \
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(rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
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RX_PKT_CMPL_FLAGS2_L4_CS_CALC | \
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RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC | \
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RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)))
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#define IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS(flags2_f) \
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((flags2_f) == \
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(rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_CS_CALC | \
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RX_PKT_CMPL_FLAGS2_L4_CS_CALC | \
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RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC)))
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#define IS_L4_TUNNEL_PKT(flags2_f) \
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( \
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IS_L4_TUNNEL_PKT_INNER_OUTER_L4_CS(flags2_f) || \
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IS_L4_TUNNEL_PKT_ONLY_INNER_L4_CS(flags2_f) \
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)
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#define BNXT_TPA_START_AGG_ID_PRE_TH(cmp) \
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((rte_le_to_cpu_16((cmp)->agg_id) & RX_TPA_START_CMPL_AGG_ID_MASK) >> \
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RX_TPA_START_CMPL_AGG_ID_SFT)
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@ -141,42 +37,11 @@ static inline uint16_t bnxt_tpa_start_agg_id(struct bnxt *bp,
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#define BNXT_TPA_END_AGG_ID_TH(cmp) \
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rte_le_to_cpu_16((cmp)->agg_id)
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#define RX_CMP_L4_CS_BITS \
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rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_L4_CS_CALC)
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#define RX_CMP_L4_CS_UNKNOWN(rxcmp1) \
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!((rxcmp1)->flags2 & RX_CMP_L4_CS_BITS)
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#define RX_CMP_T_L4_CS_BITS \
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rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC)
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#define RX_CMP_T_L4_CS_UNKNOWN(rxcmp1) \
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!((rxcmp1)->flags2 & RX_CMP_T_L4_CS_BITS)
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/* Outer L4 chksum error
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*/
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#define RX_CMP_L4_OUTER_CS_ERR2(rxcmp1) \
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((rxcmp1)->errors_v2 & \
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rte_cpu_to_le_32(RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR))
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/* Inner L4 chksum error
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*/
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#define RX_CMP_L4_INNER_CS_ERR2(rxcmp1) \
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((rxcmp1)->errors_v2 & \
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rte_cpu_to_le_32(RX_PKT_CMPL_ERRORS_L4_CS_ERROR))
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#define BNXT_RX_POST_THRESH 32
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/* Number of descriptors to process per inner loop in vector mode. */
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#define RTE_BNXT_DESCS_PER_LOOP 4U
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enum pkt_hash_types {
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PKT_HASH_TYPE_NONE, /* Undefined type */
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PKT_HASH_TYPE_L2, /* Input: src_MAC, dest_MAC */
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PKT_HASH_TYPE_L3, /* Input: src_IP, dst_IP */
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PKT_HASH_TYPE_L4, /* Input: src_IP, dst_IP, src_port, dst_port */
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};
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struct bnxt_tpa_info {
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struct rte_mbuf *mbuf;
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uint16_t len;
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@ -14,18 +14,11 @@ struct bnxt_cp_ring_info;
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struct bnxt_tx_queue {
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uint16_t nb_tx_desc; /* number of TX descriptors */
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uint16_t tx_free_thresh;/* minimum TX before freeing */
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/** Index to last TX descriptor to have been cleaned. */
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uint16_t last_desc_cleaned;
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/** Total number of TX descriptors ready to be allocated. */
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uint16_t tx_next_dd; /* next desc to scan for DD bit */
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uint16_t tx_next_rs; /* next desc to set RS bit */
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uint16_t queue_id; /* TX queue index */
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uint16_t reg_idx; /* TX queue register index */
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uint16_t port_id; /* Device port identifier */
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uint8_t pthresh; /* Prefetch threshold register */
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uint8_t hthresh; /* Host threshold register */
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uint8_t wthresh; /* Write-back threshold reg */
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uint32_t ctx_curr; /* Hardware context states */
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uint8_t tx_deferred_start; /* not in global dev start */
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uint8_t tx_started; /* TX queue is started */
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@ -8,13 +8,9 @@
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#include <rte_io.h>
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#define MAX_TX_RINGS 16
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#define BNXT_TX_PUSH_THRESH 92
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#define BNXT_MAX_TSO_SEGS 32
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#define BNXT_MIN_PKT_SIZE 52
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#define B_TX_DB(db, prod) rte_write32((DB_KEY_TX | (prod)), db)
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struct bnxt_tx_ring_info {
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uint16_t tx_prod;
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uint16_t tx_cons;
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@ -25,15 +21,11 @@ struct bnxt_tx_ring_info {
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rte_iova_t tx_desc_mapping;
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#define BNXT_DEV_STATE_CLOSING 0x1
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uint32_t dev_state;
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struct bnxt_ring *tx_ring_struct;
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};
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struct bnxt_sw_tx_bd {
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struct rte_mbuf *mbuf; /* mbuf associated with TX descriptor */
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uint8_t is_gso;
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unsigned short nr_bds;
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};
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