baseband/acc200: add HW register definitions
Added registers list and structure to access the ACC200 device. Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
This commit is contained in:
Nicolas Chautru
Akhil Goyal
parent
c2d93488c7
commit
b8f8d1aeb2
108
drivers/baseband/acc/acc200_pf_enum.h
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108
drivers/baseband/acc/acc200_pf_enum.h
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@ -0,0 +1,108 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2021 Intel Corporation
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*/
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#ifndef ACC200_PF_ENUM_H
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#define ACC200_PF_ENUM_H
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/*
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* ACC200 Register mapping on PF BAR0
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* This is automatically generated from RDL, format may change with new RDL
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* Release.
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* Variable names are as is
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*/
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enum {
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HWPfQmgrEgressQueuesTemplate = 0x0007FC00,
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HWPfQmgrIngressAq = 0x00080000,
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HWPfQmgrDepthLog2Grp = 0x00A00200,
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HWPfQmgrTholdGrp = 0x00A00300,
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HWPfQmgrGrpTmplateReg0Indx = 0x00A00600,
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HWPfQmgrGrpTmplateReg1Indx = 0x00A00700,
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HWPfQmgrGrpTmplateReg2indx = 0x00A00800,
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HWPfQmgrGrpTmplateReg3Indx = 0x00A00900,
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HWPfQmgrGrpTmplateReg4Indx = 0x00A00A00,
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HWPfQmgrVfBaseAddr = 0x00A01000,
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HWPfQmgrArbQDepthGrp = 0x00A02F00,
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HWPfQmgrGrpFunction0 = 0x00A02F40,
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HWPfQmgrGrpFunction1 = 0x00A02F44,
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HWPfQmgrGrpPriority = 0x00A02F48,
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HWPfQmgrAqEnableVf = 0x00A10000,
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HWPfQmgrRingSizeVf = 0x00A20004,
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HWPfQmgrGrpDepthLog20Vf = 0x00A20008,
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HWPfQmgrGrpDepthLog21Vf = 0x00A2000C,
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HWPfFabricM2iBufferReg = 0x00B30000,
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HWPfFabricI2Mdma_weight = 0x00B31044,
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HwPfFecUl5gIbDebugReg = 0x00B40200,
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HWPfFftConfig0 = 0x00B58004,
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HWPfFftRamPageAccess = 0x00B5800C,
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HWPfFftRamOff = 0x00B58800,
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HWPfDmaConfig0Reg = 0x00B80000,
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HWPfDmaConfig1Reg = 0x00B80004,
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HWPfDmaQmgrAddrReg = 0x00B80008,
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HWPfDmaAxcacheReg = 0x00B80010,
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HWPfDmaAxiControl = 0x00B8002C,
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HWPfDmaQmanen = 0x00B80040,
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HWPfDma4gdlIbThld = 0x00B800CC,
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HWPfDmaCfgRrespBresp = 0x00B80814,
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HWPfDmaDescriptorSignatuture = 0x00B80868,
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HWPfDmaErrorDetectionEn = 0x00B80870,
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HWPfDmaFec5GulDescBaseLoRegVf = 0x00B88020,
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HWPfDmaFec5GulDescBaseHiRegVf = 0x00B88024,
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HWPfDmaFec5GulRespPtrLoRegVf = 0x00B88028,
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HWPfDmaFec5GulRespPtrHiRegVf = 0x00B8802C,
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HWPfDmaFec5GdlDescBaseLoRegVf = 0x00B88040,
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HWPfDmaFec5GdlDescBaseHiRegVf = 0x00B88044,
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HWPfDmaFec5GdlRespPtrLoRegVf = 0x00B88048,
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HWPfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C,
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HWPfDmaFec4GulDescBaseLoRegVf = 0x00B88060,
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HWPfDmaFec4GulDescBaseHiRegVf = 0x00B88064,
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HWPfDmaFec4GulRespPtrLoRegVf = 0x00B88068,
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HWPfDmaFec4GulRespPtrHiRegVf = 0x00B8806C,
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HWPfDmaFec4GdlDescBaseLoRegVf = 0x00B88080,
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HWPfDmaFec4GdlDescBaseHiRegVf = 0x00B88084,
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HWPfDmaFec4GdlRespPtrLoRegVf = 0x00B88088,
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HWPfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C,
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HWPDmaFftDescBaseLoRegVf = 0x00B880A0,
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HWPDmaFftDescBaseHiRegVf = 0x00B880A4,
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HWPDmaFftRespPtrLoRegVf = 0x00B880A8,
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HWPDmaFftRespPtrHiRegVf = 0x00B880AC,
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HWPfQosmonAEvalOverflow0 = 0x00B90008,
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HWPfPermonACntrlRegVf = 0x00B98000,
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HWPfQosmonBEvalOverflow0 = 0x00BA0008,
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HWPfPermonBCntrlRegVf = 0x00BA8000,
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HWPfPermonCCntrlRegVf = 0x00BB8000,
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HWPfHiInfoRingBaseLoRegPf = 0x00C84014,
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HWPfHiInfoRingBaseHiRegPf = 0x00C84018,
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HWPfHiInfoRingPointerRegPf = 0x00C8401C,
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HWPfHiInfoRingIntWrEnRegPf = 0x00C84020,
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HWPfHiBlockTransmitOnErrorEn = 0x00C84038,
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HWPfHiCfgMsiIntWrEnRegPf = 0x00C84040,
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HWPfHiMsixVectorMapperPf = 0x00C84060,
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HWPfHiPfMode = 0x00C84108,
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HWPfHiClkGateHystReg = 0x00C8410C,
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HWPfHiMsiDropEnableReg = 0x00C84114,
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HWPfHiSectionPowerGatingReq = 0x00C84128,
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HWPfHiSectionPowerGatingAck = 0x00C8412C,
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};
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/* TIP PF Interrupt numbers */
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enum {
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ACC200_PF_INT_QMGR_AQ_OVERFLOW = 0,
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ACC200_PF_INT_DOORBELL_VF_2_PF = 1,
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ACC200_PF_INT_ILLEGAL_FORMAT = 2,
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ACC200_PF_INT_QMGR_DISABLED_ACCESS = 3,
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ACC200_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4,
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ACC200_PF_INT_DMA_DL_DESC_IRQ = 5,
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ACC200_PF_INT_DMA_UL_DESC_IRQ = 6,
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ACC200_PF_INT_DMA_FFT_DESC_IRQ = 7,
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ACC200_PF_INT_DMA_UL5G_DESC_IRQ = 8,
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ACC200_PF_INT_DMA_DL5G_DESC_IRQ = 9,
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ACC200_PF_INT_DMA_MLD_DESC_IRQ = 10,
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ACC200_PF_INT_ARAM_ECC_1BIT_ERR = 11,
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ACC200_PF_INT_PARITY_ERR = 12,
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ACC200_PF_INT_QMGR_ERR = 13,
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ACC200_PF_INT_INT_REQ_OVERFLOW = 14,
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ACC200_PF_INT_APB_TIMEOUT = 15,
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};
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#endif /* ACC200_PF_ENUM_H */
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@ -6,6 +6,8 @@
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#define _RTE_ACC200_PMD_H_
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#include "acc_common.h"
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#include "acc200_pf_enum.h"
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#include "acc200_vf_enum.h"
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/* Helper macro for logging */
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#define rte_bbdev_log(level, fmt, ...) \
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@ -29,4 +31,165 @@
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#define RTE_ACC200_PF_DEVICE_ID (0x57C0)
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#define RTE_ACC200_VF_DEVICE_ID (0x57C1)
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#define ACC200_MAX_PF_MSIX (256+32)
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#define ACC200_MAX_VF_MSIX (256+7)
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/* Values used in writing to the registers */
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#define ACC200_REG_IRQ_EN_ALL 0x1FF83FF /* Enable all interrupts */
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/* Number of Virtual Functions ACC200 supports */
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#define ACC200_NUM_VFS 16
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#define ACC200_NUM_QGRPS 16
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#define ACC200_NUM_AQS 16
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#define ACC200_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */
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#define ACC200_VF_ID_SHIFT 4 /* Queue Index Hierarchy */
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#define ACC200_WORDS_IN_ARAM_SIZE (256 * 1024 / 4)
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/* Mapping of signals for the available engines */
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#define ACC200_SIG_UL_5G 0
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#define ACC200_SIG_UL_5G_LAST 4
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#define ACC200_SIG_DL_5G 10
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#define ACC200_SIG_DL_5G_LAST 11
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#define ACC200_SIG_UL_4G 12
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#define ACC200_SIG_UL_4G_LAST 16
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#define ACC200_SIG_DL_4G 21
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#define ACC200_SIG_DL_4G_LAST 23
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#define ACC200_SIG_FFT 24
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#define ACC200_SIG_FFT_LAST 24
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#define ACC200_NUM_ACCS 5
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/* ACC200 Configuration */
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#define ACC200_FABRIC_MODE 0x8000103
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#define ACC200_CFG_DMA_ERROR 0x3DF
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#define ACC200_CFG_AXI_CACHE 0x11
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#define ACC200_CFG_QMGR_HI_P 0x0F0F
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#define ACC200_RESET_HARD 0x1FF
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#define ACC200_ENGINES_MAX 9
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#define ACC200_GPEX_AXIMAP_NUM 17
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#define ACC200_CLOCK_GATING_EN 0x30000
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#define ACC200_FFT_CFG_0 0x2001
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#define ACC200_FFT_RAM_EN 0x80008000
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#define ACC200_FFT_RAM_DIS 0x0
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#define ACC200_FFT_RAM_SIZE 512
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#define ACC200_CLK_EN 0x00010A01
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#define ACC200_CLK_DIS 0x01F10A01
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#define ACC200_PG_MASK_0 0x1F
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#define ACC200_PG_MASK_1 0xF
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#define ACC200_PG_MASK_2 0x1
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#define ACC200_PG_MASK_3 0x0
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#define ACC200_PG_MASK_FFT 1
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#define ACC200_PG_MASK_4GUL 4
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#define ACC200_PG_MASK_5GUL 8
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#define ACC200_STATUS_WAIT 10
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#define ACC200_STATUS_TO 100
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struct acc200_registry_addr {
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unsigned int dma_ring_dl5g_hi;
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unsigned int dma_ring_dl5g_lo;
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unsigned int dma_ring_ul5g_hi;
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unsigned int dma_ring_ul5g_lo;
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unsigned int dma_ring_dl4g_hi;
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unsigned int dma_ring_dl4g_lo;
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unsigned int dma_ring_ul4g_hi;
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unsigned int dma_ring_ul4g_lo;
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unsigned int dma_ring_fft_hi;
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unsigned int dma_ring_fft_lo;
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unsigned int ring_size;
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unsigned int info_ring_hi;
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unsigned int info_ring_lo;
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unsigned int info_ring_en;
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unsigned int info_ring_ptr;
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unsigned int tail_ptrs_dl5g_hi;
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unsigned int tail_ptrs_dl5g_lo;
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unsigned int tail_ptrs_ul5g_hi;
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unsigned int tail_ptrs_ul5g_lo;
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unsigned int tail_ptrs_dl4g_hi;
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unsigned int tail_ptrs_dl4g_lo;
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unsigned int tail_ptrs_ul4g_hi;
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unsigned int tail_ptrs_ul4g_lo;
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unsigned int tail_ptrs_fft_hi;
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unsigned int tail_ptrs_fft_lo;
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unsigned int depth_log0_offset;
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unsigned int depth_log1_offset;
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unsigned int qman_group_func;
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unsigned int hi_mode;
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unsigned int pmon_ctrl_a;
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unsigned int pmon_ctrl_b;
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unsigned int pmon_ctrl_c;
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};
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/* Structure holding registry addresses for PF */
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static const struct acc200_registry_addr pf_reg_addr = {
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.dma_ring_dl5g_hi = HWPfDmaFec5GdlDescBaseHiRegVf,
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.dma_ring_dl5g_lo = HWPfDmaFec5GdlDescBaseLoRegVf,
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.dma_ring_ul5g_hi = HWPfDmaFec5GulDescBaseHiRegVf,
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.dma_ring_ul5g_lo = HWPfDmaFec5GulDescBaseLoRegVf,
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.dma_ring_dl4g_hi = HWPfDmaFec4GdlDescBaseHiRegVf,
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.dma_ring_dl4g_lo = HWPfDmaFec4GdlDescBaseLoRegVf,
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.dma_ring_ul4g_hi = HWPfDmaFec4GulDescBaseHiRegVf,
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.dma_ring_ul4g_lo = HWPfDmaFec4GulDescBaseLoRegVf,
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.dma_ring_fft_hi = HWPDmaFftDescBaseHiRegVf,
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.dma_ring_fft_lo = HWPDmaFftDescBaseLoRegVf,
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.ring_size = HWPfQmgrRingSizeVf,
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.info_ring_hi = HWPfHiInfoRingBaseHiRegPf,
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.info_ring_lo = HWPfHiInfoRingBaseLoRegPf,
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.info_ring_en = HWPfHiInfoRingIntWrEnRegPf,
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.info_ring_ptr = HWPfHiInfoRingPointerRegPf,
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.tail_ptrs_dl5g_hi = HWPfDmaFec5GdlRespPtrHiRegVf,
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.tail_ptrs_dl5g_lo = HWPfDmaFec5GdlRespPtrLoRegVf,
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.tail_ptrs_ul5g_hi = HWPfDmaFec5GulRespPtrHiRegVf,
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.tail_ptrs_ul5g_lo = HWPfDmaFec5GulRespPtrLoRegVf,
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.tail_ptrs_dl4g_hi = HWPfDmaFec4GdlRespPtrHiRegVf,
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.tail_ptrs_dl4g_lo = HWPfDmaFec4GdlRespPtrLoRegVf,
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.tail_ptrs_ul4g_hi = HWPfDmaFec4GulRespPtrHiRegVf,
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.tail_ptrs_ul4g_lo = HWPfDmaFec4GulRespPtrLoRegVf,
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.tail_ptrs_fft_hi = HWPDmaFftRespPtrHiRegVf,
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.tail_ptrs_fft_lo = HWPDmaFftRespPtrLoRegVf,
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.depth_log0_offset = HWPfQmgrGrpDepthLog20Vf,
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.depth_log1_offset = HWPfQmgrGrpDepthLog21Vf,
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.qman_group_func = HWPfQmgrGrpFunction0,
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.hi_mode = HWPfHiMsixVectorMapperPf,
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.pmon_ctrl_a = HWPfPermonACntrlRegVf,
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.pmon_ctrl_b = HWPfPermonBCntrlRegVf,
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.pmon_ctrl_c = HWPfPermonCCntrlRegVf,
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};
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/* Structure holding registry addresses for VF */
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static const struct acc200_registry_addr vf_reg_addr = {
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.dma_ring_dl5g_hi = HWVfDmaFec5GdlDescBaseHiRegVf,
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.dma_ring_dl5g_lo = HWVfDmaFec5GdlDescBaseLoRegVf,
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.dma_ring_ul5g_hi = HWVfDmaFec5GulDescBaseHiRegVf,
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.dma_ring_ul5g_lo = HWVfDmaFec5GulDescBaseLoRegVf,
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.dma_ring_dl4g_hi = HWVfDmaFec4GdlDescBaseHiRegVf,
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.dma_ring_dl4g_lo = HWVfDmaFec4GdlDescBaseLoRegVf,
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.dma_ring_ul4g_hi = HWVfDmaFec4GulDescBaseHiRegVf,
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.dma_ring_ul4g_lo = HWVfDmaFec4GulDescBaseLoRegVf,
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.dma_ring_fft_hi = HWVfDmaFftDescBaseHiRegVf,
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.dma_ring_fft_lo = HWVfDmaFftDescBaseLoRegVf,
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.ring_size = HWVfQmgrRingSizeVf,
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.info_ring_hi = HWVfHiInfoRingBaseHiVf,
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.info_ring_lo = HWVfHiInfoRingBaseLoVf,
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.info_ring_en = HWVfHiInfoRingIntWrEnVf,
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.info_ring_ptr = HWVfHiInfoRingPointerVf,
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.tail_ptrs_dl5g_hi = HWVfDmaFec5GdlRespPtrHiRegVf,
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.tail_ptrs_dl5g_lo = HWVfDmaFec5GdlRespPtrLoRegVf,
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.tail_ptrs_ul5g_hi = HWVfDmaFec5GulRespPtrHiRegVf,
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.tail_ptrs_ul5g_lo = HWVfDmaFec5GulRespPtrLoRegVf,
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.tail_ptrs_dl4g_hi = HWVfDmaFec4GdlRespPtrHiRegVf,
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.tail_ptrs_dl4g_lo = HWVfDmaFec4GdlRespPtrLoRegVf,
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.tail_ptrs_ul4g_hi = HWVfDmaFec4GulRespPtrHiRegVf,
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.tail_ptrs_ul4g_lo = HWVfDmaFec4GulRespPtrLoRegVf,
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.tail_ptrs_fft_hi = HWVfDmaFftRespPtrHiRegVf,
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.tail_ptrs_fft_lo = HWVfDmaFftRespPtrLoRegVf,
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.depth_log0_offset = HWVfQmgrGrpDepthLog20Vf,
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.depth_log1_offset = HWVfQmgrGrpDepthLog21Vf,
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.qman_group_func = HWVfQmgrGrpFunction0Vf,
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.hi_mode = HWVfHiMsixVectorMapperVf,
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.pmon_ctrl_a = HWVfPmACntrlRegVf,
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.pmon_ctrl_b = HWVfPmBCntrlRegVf,
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.pmon_ctrl_c = HWVfPmCCntrlRegVf,
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};
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#endif /* _RTE_ACC200_PMD_H_ */
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83
drivers/baseband/acc/acc200_vf_enum.h
Normal file
83
drivers/baseband/acc/acc200_vf_enum.h
Normal file
@ -0,0 +1,83 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2021 Intel Corporation
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*/
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#ifndef ACC200_VF_ENUM_H
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#define ACC200_VF_ENUM_H
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/*
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* ACC200 Register mapping on VF BAR0
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* This is automatically generated from RDL, format may change with new RDL
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*/
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enum {
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HWVfQmgrIngressAq = 0x00000000,
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HWVfHiVfToPfDbellVf = 0x00000800,
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HWVfHiPfToVfDbellVf = 0x00000808,
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HWVfHiInfoRingBaseLoVf = 0x00000810,
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HWVfHiInfoRingBaseHiVf = 0x00000814,
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HWVfHiInfoRingPointerVf = 0x00000818,
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HWVfHiInfoRingIntWrEnVf = 0x00000820,
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HWVfHiInfoRingPf2VfWrEnVf = 0x00000824,
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HWVfHiMsixVectorMapperVf = 0x00000860,
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HWVfDmaFec5GulDescBaseLoRegVf = 0x00000920,
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HWVfDmaFec5GulDescBaseHiRegVf = 0x00000924,
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HWVfDmaFec5GulRespPtrLoRegVf = 0x00000928,
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HWVfDmaFec5GulRespPtrHiRegVf = 0x0000092C,
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HWVfDmaFec5GdlDescBaseLoRegVf = 0x00000940,
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HWVfDmaFec5GdlDescBaseHiRegVf = 0x00000944,
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HWVfDmaFec5GdlRespPtrLoRegVf = 0x00000948,
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HWVfDmaFec5GdlRespPtrHiRegVf = 0x0000094C,
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HWVfDmaFec4GulDescBaseLoRegVf = 0x00000960,
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HWVfDmaFec4GulDescBaseHiRegVf = 0x00000964,
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HWVfDmaFec4GulRespPtrLoRegVf = 0x00000968,
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HWVfDmaFec4GulRespPtrHiRegVf = 0x0000096C,
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HWVfDmaFec4GdlDescBaseLoRegVf = 0x00000980,
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HWVfDmaFec4GdlDescBaseHiRegVf = 0x00000984,
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HWVfDmaFec4GdlRespPtrLoRegVf = 0x00000988,
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HWVfDmaFec4GdlRespPtrHiRegVf = 0x0000098C,
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HWVfDmaFftDescBaseLoRegVf = 0x000009A0,
|
||||
HWVfDmaFftDescBaseHiRegVf = 0x000009A4,
|
||||
HWVfDmaFftRespPtrLoRegVf = 0x000009A8,
|
||||
HWVfDmaFftRespPtrHiRegVf = 0x000009AC,
|
||||
HWVfQmgrAqResetVf = 0x00000E00,
|
||||
HWVfQmgrRingSizeVf = 0x00000E04,
|
||||
HWVfQmgrGrpDepthLog20Vf = 0x00000E08,
|
||||
HWVfQmgrGrpDepthLog21Vf = 0x00000E0C,
|
||||
HWVfQmgrGrpFunction0Vf = 0x00000E10,
|
||||
HWVfQmgrGrpFunction1Vf = 0x00000E14,
|
||||
HWVfPmACntrlRegVf = 0x00000F40,
|
||||
HWVfPmACountVf = 0x00000F48,
|
||||
HWVfPmAKCntLoVf = 0x00000F50,
|
||||
HWVfPmAKCntHiVf = 0x00000F54,
|
||||
HWVfPmADeltaCntLoVf = 0x00000F60,
|
||||
HWVfPmADeltaCntHiVf = 0x00000F64,
|
||||
HWVfPmBCntrlRegVf = 0x00000F80,
|
||||
HWVfPmBCountVf = 0x00000F88,
|
||||
HWVfPmBKCntLoVf = 0x00000F90,
|
||||
HWVfPmBKCntHiVf = 0x00000F94,
|
||||
HWVfPmBDeltaCntLoVf = 0x00000FA0,
|
||||
HWVfPmBDeltaCntHiVf = 0x00000FA4,
|
||||
HWVfPmCCntrlRegVf = 0x00000FC0,
|
||||
HWVfPmCCountVf = 0x00000FC8,
|
||||
HWVfPmCKCntLoVf = 0x00000FD0,
|
||||
HWVfPmCKCntHiVf = 0x00000FD4,
|
||||
HWVfPmCDeltaCntLoVf = 0x00000FE0,
|
||||
HWVfPmCDeltaCntHiVf = 0x00000FE4
|
||||
};
|
||||
|
||||
/* TIP VF Interrupt numbers */
|
||||
enum {
|
||||
ACC200_VF_INT_QMGR_AQ_OVERFLOW = 0,
|
||||
ACC200_VF_INT_DOORBELL_PF_2_VF = 1,
|
||||
ACC200_VF_INT_ILLEGAL_FORMAT = 2,
|
||||
ACC200_VF_INT_QMGR_DISABLED_ACCESS = 3,
|
||||
ACC200_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4,
|
||||
ACC200_VF_INT_DMA_DL_DESC_IRQ = 5,
|
||||
ACC200_VF_INT_DMA_UL_DESC_IRQ = 6,
|
||||
ACC200_VF_INT_DMA_FFT_DESC_IRQ = 7,
|
||||
ACC200_VF_INT_DMA_UL5G_DESC_IRQ = 8,
|
||||
ACC200_VF_INT_DMA_DL5G_DESC_IRQ = 9,
|
||||
ACC200_VF_INT_DMA_MLD_DESC_IRQ = 10,
|
||||
};
|
||||
|
||||
#endif /* ACC200_VF_ENUM_H */
|
||||
Loading…
Reference in New Issue
Block a user