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net/i40e: add debug logs when writing global registers

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Add debug logs when writing global registers.

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
This commit is contained in:
Beilei Xing 2018-02-02 20:05:50 +08:00 committed by Ferruh Yigit
parent 399c635c39
commit bc66b9717c
2 changed files with 123 additions and 41 deletions
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153
drivers/net/i40e/i40e_ethdev.c
View File

@ -656,6 +656,15 @@ rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
return 0;
}
static inline void
i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
{
i40e_write_rx_ctl(hw, reg_addr, reg_val);
PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
"with value 0x%08x",
reg_addr, reg_val);
}
RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
@ -678,8 +687,8 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
* configuration API is added to avoid configuration conflicts
* between ports of the same device.
*/
I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
}
@ -1134,6 +1143,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
0x00000028, NULL);
if (ret)
PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
PMD_INIT_LOG(DEBUG, "Global register 0x%08x is changed with value 0x28",
I40E_GLQF_L3_MAP(40));
i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
/* Need the special FW version to support floating VEB */
@ -1412,9 +1423,9 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
* Disable by default flexible payload
* for corresponding L2/L3/L4 layers.
*/
I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
}
@ -3221,8 +3232,8 @@ i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
return -EIO;
}
PMD_DRV_LOG(DEBUG,
"Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
reg_w, reg_id);
"Global register 0x%08x is changed with value 0x%08x",
I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
return 0;
}
@ -3496,16 +3507,16 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
}
/* config the water marker both based on the packets and bytes */
I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
(pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
<< I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
(pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
<< I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
<< I40E_KILOSHIFT);
I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
<< I40E_KILOSHIFT);
i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
@ -7291,8 +7302,13 @@ i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!status)
if (!status) {
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
PMD_DRV_LOG(DEBUG, "Global configuration modification: "
"cloud l1 type is changed from 0x%x to 0x%x",
filter_replace.old_filter_type,
filter_replace.new_filter_type);
}
return status;
}
@ -7325,6 +7341,10 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
&filter_replace_buf);
if (status < 0)
return status;
PMD_DRV_LOG(DEBUG, "Global configuration modification: "
"cloud filter type is changed from 0x%x to 0x%x",
filter_replace.old_filter_type,
filter_replace.new_filter_type);
/* For MPLSoGRE */
memset(&filter_replace, 0,
@ -7347,8 +7367,13 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!status)
if (!status) {
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
PMD_DRV_LOG(DEBUG, "Global configuration modification: "
"cloud filter type is changed from 0x%x to 0x%x",
filter_replace.old_filter_type,
filter_replace.new_filter_type);
}
return status;
}
@ -7388,6 +7413,10 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
&filter_replace_buf);
if (status < 0)
return status;
PMD_DRV_LOG(DEBUG, "Global configuration modification: "
"cloud l1 type is changed from 0x%x to 0x%x",
filter_replace.old_filter_type,
filter_replace.new_filter_type);
/* for GTP-U */
memset(&filter_replace, 0,
@ -7416,8 +7445,13 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!status)
if (!status) {
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
PMD_DRV_LOG(DEBUG, "Global configuration modification: "
"cloud l1 type is changed from 0x%x to 0x%x",
filter_replace.old_filter_type,
filter_replace.new_filter_type);
}
return status;
}
@ -7449,6 +7483,10 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
&filter_replace_buf);
if (status < 0)
return status;
PMD_DRV_LOG(DEBUG, "Global configuration modification: "
"cloud filter type is changed from 0x%x to 0x%x",
filter_replace.old_filter_type,
filter_replace.new_filter_type);
/* for GTP-U */
memset(&filter_replace, 0,
@ -7470,8 +7508,13 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!status)
if (!status) {
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
PMD_DRV_LOG(DEBUG, "Global configuration modification: "
"cloud filter type is changed from 0x%x to 0x%x",
filter_replace.old_filter_type,
filter_replace.new_filter_type);
}
return status;
}
@ -8021,6 +8064,9 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
reg, NULL);
if (ret != 0)
return ret;
PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
"with value 0x%08x",
I40E_GL_PRS_FVBM(2), reg);
i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
} else {
ret = 0;
@ -8277,7 +8323,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
for (j = I40E_FILTER_PCTYPE_INVALID + 1;
j < I40E_FILTER_PCTYPE_MAX; j++) {
if (adapter->pctypes_tbl[i] & (1ULL << j))
i40e_write_rx_ctl(hw,
i40e_write_global_rx_ctl(hw,
I40E_GLQF_HSYM(j),
reg);
}
@ -8306,7 +8352,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
/* Use the default, and keep it as it is */
goto out;
i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
out:
@ -8896,6 +8942,18 @@ i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
(uint32_t)i40e_read_rx_ctl(hw, addr));
}
void
i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
{
uint32_t reg = i40e_read_rx_ctl(hw, addr);
PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
if (reg != val)
i40e_write_global_rx_ctl(hw, addr, val);
PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
(uint32_t)i40e_read_rx_ctl(hw, addr));
}
static void
i40e_filter_input_set_init(struct i40e_pf *pf)
{
@ -8927,24 +8985,28 @@ i40e_filter_input_set_init(struct i40e_pf *pf)
i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
(uint32_t)((inset_reg >>
I40E_32_BIT_WIDTH) & UINT32_MAX));
i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
(uint32_t)(inset_reg & UINT32_MAX));
i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
(uint32_t)((inset_reg >>
I40E_32_BIT_WIDTH) & UINT32_MAX));
for (i = 0; i < num; i++) {
i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
mask_reg[i]);
i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
mask_reg[i]);
i40e_check_write_global_reg(hw,
I40E_GLQF_FD_MSK(i, pctype),
mask_reg[i]);
i40e_check_write_global_reg(hw,
I40E_GLQF_HASH_MSK(i, pctype),
mask_reg[i]);
}
/*clear unused mask registers of the pctype */
for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
0);
i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
0);
i40e_check_write_global_reg(hw,
I40E_GLQF_FD_MSK(i, pctype),
0);
i40e_check_write_global_reg(hw,
I40E_GLQF_HASH_MSK(i, pctype),
0);
}
I40E_WRITE_FLUSH(hw);
@ -9011,20 +9073,20 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
(uint32_t)(inset_reg & UINT32_MAX));
i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
(uint32_t)((inset_reg >>
I40E_32_BIT_WIDTH) & UINT32_MAX));
i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
(uint32_t)(inset_reg & UINT32_MAX));
i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
(uint32_t)((inset_reg >>
I40E_32_BIT_WIDTH) & UINT32_MAX));
i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
for (i = 0; i < num; i++)
i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
mask_reg[i]);
i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
mask_reg[i]);
/*clear unused mask registers of the pctype */
for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
0);
i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
0);
i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
I40E_WRITE_FLUSH(hw);
@ -9093,12 +9155,12 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,
I40E_32_BIT_WIDTH) & UINT32_MAX));
for (i = 0; i < num; i++)
i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
mask_reg[i]);
i40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
mask_reg[i]);
/*clear unused mask registers of the pctype */
for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
0);
i40e_check_write_global_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
0);
i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
I40E_WRITE_FLUSH(hw);
@ -11646,6 +11708,10 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
&filter_replace_buf);
if (ret != I40E_SUCCESS)
return ret;
PMD_DRV_LOG(DEBUG, "Global configuration modification: "
"cloud l1 type is changed from 0x%x to 0x%x",
filter_replace.old_filter_type,
filter_replace.new_filter_type);
/* Apply the second L2 cloud filter */
memset(&filter_replace, 0,
@ -11667,8 +11733,13 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!ret)
if (!ret) {
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
PMD_DRV_LOG(DEBUG, "Global configuration modification: "
"cloud filter type is changed from 0x%x to 0x%x",
filter_replace.old_filter_type,
filter_replace.new_filter_type);
}
return ret;
}

11
drivers/net/i40e/i40e_ethdev.h
View File

@ -78,6 +78,15 @@
(((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
((vf)->version_minor == 1))
#define I40E_WRITE_GLB_REG(hw, reg, value) \
do { \
I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), \
(reg)), (value)); \
PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified " \
"with value 0x%08x", \
(reg), (value)); \
} while (0)
/* index flex payload per layer */
enum i40e_flxpld_layer_idx {
I40E_FLXPLD_L2_IDX = 0,
@ -1187,6 +1196,8 @@ int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
uint8_t nb_elem);
uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
void i40e_check_write_global_reg(struct i40e_hw *hw,
uint32_t addr, uint32_t val);
int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
void i40e_tm_conf_init(struct rte_eth_dev *dev);